Laterally diffused metal oxide semiconductor with gate poly contact within source window

• US 10,103,258 B2
• Filed: 12/29/2016
• Issued: 10/16/2018
• Est. Priority Date: 12/29/2016
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Pendharkar, Sameer, Mathur, Guru
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US15/394,636
• Publication Number:
  US 20180190814A1
• Time in Patent Office: 656 Days
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

Claims

1. An integrated circuit comprising:

a semiconductor material substrate;

a power transistor having at least one transistor finger that lies within the semiconductor material substrate, each transistor finger including;

a source region stripe;

a drain region stripe substantially parallel to the source region stripe;

a channel region stripe located substantially parallel to and between the source region stripe and the drain region stripe;

a gate oxide that overlies the channel region stripe;

spaced apart thick oxide islands that overlie the source region stripe;

a gate structure that overlies the gate oxide and the thick oxide islands, in which contacts are connected to the gate structure over the thick oxide islands; and

a conductive gate runner connected to the contacts of the gate structure over the thick oxide islands.

2. The integrated circuit of claim 1, in which the gate structure comprises polysilicon.

3. The integrated circuit of claim 1, in which the power transistor is a laterally diffused metal oxide semiconductor device having an extension of the gate structure connected to the source region stripe.

4. The integrated circuit of claim 1, in which the at least one transistor finger has a linear topology.

5. The integrated circuit of claim 1, in which the conductive gate runner is arranged perpendicularly to the source region stripe.

6. The integrated circuit of claim 1, further including control circuitry that lies within the semiconductor material substrate with at least one output signal coupled to the gate structure.

7. An integrated circuit comprising:

a semiconductor material substrate;

a power transistor having at least one transistor finger that lies within the semiconductor material substrate, each transistor finger including;

a source region stripe;

a drain region stripe substantially parallel to the source region stripe;

a gate structure that lies between the source region stripe and the drain region stripe, the gate structure having a plurality of extensions that extend over the source region stripe;

contacts connected to the extensions of the gate structure over the source region stripes; and

a conductive gate runner connected to the contacts of the gate structure over the source region stripe.

8. The integrated circuit of claim 7, further including a separate thick oxide island located in the source region stripe below the contacts of each extension of the gate structure.

9. The integrated circuit of claim 7, in which the gate structure comprises polysilicon.

10. The integrated circuit of claim 7, in which the conductive gate runner is arranged perpendicularly to the source region stripe.

11. The power transistor of claim 7, in which the power transistor is a laterally diffused metal oxide semiconductor device having an extended region connected to the drain region stripe.

12. The integrated circuit of claim 7, in which the at least one transistor finger has a linear topology.

13. The integrated circuit of claim 7, further including control circuitry that lies within the semiconductor material substrate with at least one output signal coupled to the gate structure.