Semiconductor device and method for manufacturing the same

• US 10,103,272 B2
• Filed: 10/19/2015
• Issued: 10/16/2018
• Est. Priority Date: 12/11/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sakata, Junichiro, Maruyama, Tetsunori, Imoto, Yuki
• Primary Examiner(s): Mandala, Victor A
• Assistant Examiner(s): Snow, Colleen E
• Application Number:
  US14/886,723
• Publication Number:
  US 20160043230A1
• Time in Patent Office: 1,093 Days
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Many of the physical properties of a silicon semiconductor have already been understood, whereas many of the physical properties of an oxide semiconductor have been still unclear. In particular, an adverse effect of an impurity on an oxide semiconductor has been still unclear. In view of the above, a structure is disclosed in which an impurity that influences electrical characteristics of a semiconductor device including an oxide semiconductor layer is prevented or is eliminated. A semiconductor device which includes a gate electrode, an oxide semiconductor layer, and a gate insulating layer provided between the gate electrode and the oxide semiconductor layer and in which the nitrogen concentration in the oxide semiconductor layer is 1×10²⁰ atoms/cm³ or less is provided.

Claims

1. A semiconductor device comprising:

a substrate;

an oxide semiconductor layer over the substrate;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode over the gate insulating layer;

an insulating layer over the gate electrode;

a first wiring electrically connected to the gate electrode through a first contact hole which is provided in the insulating layer;

a second wiring electrically connected to a first region of the oxide semiconductor layer through a second contact hole which is provided in the gate insulating layer and the insulating layer; and

a third wiring electrically connected to a second region of the oxide semiconductor layer through a third contact hole which is provided in the gate insulating layer and the insulating layer,

wherein a nitrogen concentration in the oxide semiconductor layer is 1×

10¹⁸ atoms/cm³ or less.

2. The semiconductor device according to claim 1, wherein a hydrogen concentration in the oxide semiconductor layer is 6×

10¹⁸ atoms/cm³ or less.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is in an oxygen-excess state.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises indium, tin, and zinc.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises tin, gallium, and zinc.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is formed by sputtering using a target having an atomic ratio of In:

Ga;

Zn=1;

1;

0.5.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is formed by sputtering using a target having an atomic ratio of In:

Ga;

Zn=1;

1;

1.

9. The semiconductor device according to claim 1, wherein each of the first region and the second region comprises titanium oxide.

10. A semiconductor device comprising:

a substrate;

an oxide semiconductor layer over the substrate;

a pair of contact electrodes electrically connected to the oxide semiconductor layer;

a gate insulating layer over the oxide semiconductor layer;

a gate electrode over the gate insulating layer;

an insulating layer over the gate electrode and the pair of contact electrodes; and

a transistor over the insulating layer,

wherein a nitrogen concentration in the oxide semiconductor layer is 1×

10¹⁸ atoms/cm³ or less.

11. The semiconductor device according to claim 10, wherein a hydrogen concentration in the oxide semiconductor layer is 6×

10¹⁸ atoms/cm³ or less.

12. The semiconductor device according to claim 10, wherein the oxide semiconductor layer is in an oxygen-excess state.

13. The semiconductor device according to claim 10, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

14. The semiconductor device according to, claim 10, wherein the oxide semiconductor layer comprises indium, tin, and zinc.

15. The semiconductor device according to claim 10, wherein the oxide semiconductor layer comprises tin, gallium, and zinc.

16. The semiconductor device according to claim 10, wherein the oxide semiconductor layer is formed by sputtering using a target having an atomic ratio of In:

Ga;

Zn=1;

1;

0.5.

17. The semiconductor device according to claim 10, wherein the oxide semiconductor layer is formed by sputtering using a target having an atomic ratio of In:

Ga;

Zn=1;

1;

1.

18. A semiconductor device comprising:

a substrate;

a gate electrode over the substrate;

a gate insulating layer over the gate electrode;

an oxide semiconductor layer over the gate insulating layer;

a pair of contact electrodes electrically connected to the oxide semiconductor layer;

an insulating layer over the oxide semiconductor layer and the pair of contact electrodes; and

a transistor over the insulating layer,

wherein a nitrogen concentration in the oxide semiconductor layer is 1×

10¹⁸ atoms/cm³ or less.

19. The semiconductor device according to claim 18, further comprising a channel protective layer over the oxide semiconductor layer,

wherein the pair of contact electrodes is over the oxide semiconductor layer and the channel protective layer.

20. The semiconductor device according to claim 18, wherein a hydrogen concentration in the oxide semiconductor layer is 6×

10¹⁸ atoms/cm³ or less.

21. The semiconductor device according to claim 18, wherein the oxide semiconductor layer is in an oxygen-excess state.

22. The semiconductor device according to claim 18, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

23. The semiconductor device according to claim 18, wherein the oxide semiconductor layer comprises indium, tin, and zinc.

24. The semiconductor device according to claim 18, wherein the oxide semiconductor layer comprises tin, gallium, and zinc.

25. The semiconductor device according to claim 18, wherein the oxide semiconductor layer is formed by sputtering using a target having an atomic ratio of In:

Ga;

Zn=1;

1;

0.5.

26. The semiconductor device according to claim 18, wherein the oxide semiconductor layer is formed by sputtering using a target having an atomic ratio of In:

Ga;

Zn=1;

1;

1.