Low power voltage level shifter circuit
First Claim
1. A voltage level shifter circuit comprising:
- a first MOS (metal-oxide-semiconductor) transistor having a set current passing through the first MOS transistor;
a first CMOS (complementary metal-oxide-semiconductor) logic circuit receiving input signals within a first voltage level and connected between a first upper power supply and a first lower power supply;
a second CMOS logic circuit transmitting shifted output signals, the shifted output signals within a second voltage level, and directly connected between at least two current-limiting MOS transistors and a second upper power supply or a second lower power supply; and
the at least two current-limiting MOS transistors connected between the second CMOS logic circuit and the second upper power supply or the second lower power supply, currents through the current-limiting MOS transistors mirroring the set current through the first MOS transistor.
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Accused Products
Abstract
A low power voltage level shifter circuit in which current is limited through at least one of a plurality of CMOS logic circuits, one of which receives input signals within a first voltage level and is connected between a first upper and lower power supply, a second of which transmits shifted output signals within a second voltage level and is connected between a second upper and lower power supply. There is at least one current-limiting MOS transistor connected between at one of the CMOS logic circuits and one of its power supplies. Typically, there is at least one current-limiting MOS transistor between the second CMOS logic circuit which transmits the shifted output signals which have a larger range than that of the input signals. A second current through the at least one current-limiting MOS transistor mirrors a set current through a first MOS transistor so that power consumed by the CMOS logic circuit during switching is limited.
15 Citations
32 Claims
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1. A voltage level shifter circuit comprising:
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a first MOS (metal-oxide-semiconductor) transistor having a set current passing through the first MOS transistor; a first CMOS (complementary metal-oxide-semiconductor) logic circuit receiving input signals within a first voltage level and connected between a first upper power supply and a first lower power supply; a second CMOS logic circuit transmitting shifted output signals, the shifted output signals within a second voltage level, and directly connected between at least two current-limiting MOS transistors and a second upper power supply or a second lower power supply; and the at least two current-limiting MOS transistors connected between the second CMOS logic circuit and the second upper power supply or the second lower power supply, currents through the current-limiting MOS transistors mirroring the set current through the first MOS transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A method of operating a voltage level shifter circuit, the voltage level shifter circuit having a first CMOS (complementary metal-oxide-semiconductor) logic circuit receiving input signals within a first voltage level, and a second CMOS logic circuit transmitting shifted output signals within a second voltage level, the method comprising:
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generating a set current; passing the set current through a first MOS (metal-oxide-semiconductor) transistor; mirroring the set current through the first MOS transistor with currents through at least two current-limiting MOS transistors; and driving the second CMOS logic circuit with the currents, the second CMOS logic circuit directly connected between the at least two current-limiting MOS transistors and a first upper power supply or a first lower power supply. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24. An integrated circuit voltage level shifter circuit comprising:
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a first voltage level logic circuit receiving signals within a first voltage level, the first voltage level logic circuit operating within the first voltage level and connected to a first voltage power supply; a shifting logic circuit receiving signals from the first voltage level logic circuit and shifting first logic level signals to second logic level signals; a second voltage level logic circuit receiving shifted signals from the shifting logic circuit, the second voltage level logic circuit operating within a second voltage level and connected to a second voltage power supply; a bias voltage generator circuit; and two current-limiting MOS (metal-oxide-semiconductor) transistors connected between the second voltage level logic circuit and the second voltage power supply, the current-limiting MOS transistors responsive to a bias voltage from the bias voltage generator circuit to provide limited currents through the second voltage level logic circuit to limit an amount of power consumed by the second voltage level logic circuit during switching. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32)
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Specification