Semiconductor integrated circuit with a regulator circuit provided between an input terminal and an output terminal thereof

• US 10,108,209 B2
• Filed: 09/09/2015
• Issued: 10/23/2018
• Est. Priority Date: 02/13/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Inventors: Ideno, Hiroyuki, Kushibe, Hidefumi
• Primary Examiner(s): Tran, Thienvu
• Assistant Examiner(s): Bellido, Nicolas
• Application Number:
  US14/848,851
• Publication Number:
  US 20160239029A1
• Time in Patent Office: 1,140 Days
• Field of Search: 361261
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: H02H 9/04 responsive to excess voltage lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

According to one embodiment, there is provided a semiconductor integrated circuit including an output transistor, an error amplifier, and a control circuit. The output transistor is connected between a first node on an input terminal side and a second node on an output terminal side. The error amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is connected to a third node between the second node and a standard potential. The inverting input terminal is connected to a reference voltage. The output terminal is connected to the gate of the output transistor. The control circuit makes responsiveness of the error amplifier at startup slower than responsiveness of the error amplifier at steady operation.

Claims

1. A semiconductor integrated circuit comprising:

an output transistor connected between a first node on an input terminal side and a second node on an output terminal side;

an error amplifier that has a non-inverting input terminal, an inverting input terminal, and an output terminal, the non-inverting input terminal being connected to a third node between the second node and a standard potential, the inverting input terminal being connected to a reference voltage, the output terminal being connected to a gate of the output transistor; and

a control circuit that makes responsiveness of the error amplifier at startup slower than responsiveness of the error amplifier at steady operation,

wherein the control circuit compares the voltage on the output terminal and a threshold and controls the responsiveness of the error amplifier according to a comparison result, and

wherein if the voltage on the output terminal is less than or equal to the threshold, the control circuit controls the responsiveness of the error amplifier to be at first responsiveness and, if the voltage on the output terminal exceeds the threshold, controls the responsiveness of the error amplifier to be at second responsiveness faster than the first responsiveness.

2. The semiconductor integrated circuit according to claim 1, further comprising:

a variable current source connected to the error amplifier,

wherein the control circuit makes a current supplied from the variable current source to the error amplifier at startup smaller than a current supplied from the variable current source to the error amplifier at steady operation.

3. The semiconductor integrated circuit according to claim 1, further comprising:

a variable current source connected to the error amplifier,

wherein the control circuit compares the voltage on the output terminal and a threshold and controls the variable current source according to a comparison result.

4. The semiconductor integrated circuit according to claim 3, wherein if the voltage on the output terminal is less than or equal to the threshold, the control circuit controls the value of the current supplied from the variable current source to the error amplifier to be at a first value and, if the voltage on the output terminal exceeds the threshold, controls the value of the current supplied from the variable current source to the error amplifier to be at a second value greater than the first value.

15. The semiconductor integrated circuit according to claim 1, wherein an ESD (Electrostatic Discharge) protection circuit is connected to an output line, the output line connecting the second node and the output terminal.

5. A semiconductor integrated circuit comprising:

an output circuit connected between a first node on an input terminal side and a second node on an output terminal side, circuit resistance between the first node and the second node being able to be switched;

an error amplifier that has a non-inverting input terminal, an inverting input terminal, and an output terminal, the non-inverting input terminal being connected to a third node between the second node and a standard potential, the inverting input terminal being connected to a reference voltage, and the output terminal being connected to the output circuit; and

a control circuit that makes circuit resistance of the output circuit at startup higher than circuit resistance of the output circuit at steady operation,

wherein the control circuit compares the voltage on the output terminal and a threshold and controls the circuit resistance of the output circuit according to a comparison result, and

wherein if the voltage on the output terminal is less than or equal to the threshold, the control circuit controls the circuit resistance of the output circuit to be at a first value and, if the voltage on the output terminal exceeds the threshold, controls the circuit resistance of the output circuit to be at a second value lower than the first value.

9. The semiconductor integrated circuit according to claim 5,

wherein the output circuit has:

an output transistor connected between the first node and the second node;

a first switch connected in series to the output transistor between the first node and the second node;

a second resistor connected in parallel with the output transistor between the first node and the second node; and

a second switch connected in series to the second resistor between the first node and the second node, and

wherein the control circuit compares the voltage on the output terminal and the threshold and controls the on/off of each of the first switch and the second switch according to the comparison result.

10. The semiconductor integrated circuit according to claim 9, wherein if the voltage on the output terminal is less than or equal to the threshold, the control circuit controls the first switch to be off and the second switch to be on and, if the voltage on the output terminal exceeds the threshold, controls the first switch to be on and the second switch to be off.

11. The semiconductor integrated circuit according to claim 9, wherein the second resistor is a variable resistor.

12. The semiconductor integrated circuit according to claim 5,

wherein the output circuit has:

a first output transistor connected between the first node and the second node;

a second output transistor connected in parallel with the first output transistor between the first node and the second node; and

a third switch connected in series to the second output transistor between the first node and the second node, and

wherein the control circuit compares the voltage on the output terminal and the threshold and controls the on/off of the third switch according to the comparison result.

13. The semiconductor integrated circuit according to claim 12, wherein if the voltage on the output terminal is less than or equal to the threshold, the control circuit controls the third switch to be off and, if the voltage on the output terminal exceeds the threshold, controls the third switch to be on.

14. The semiconductor integrated circuit according to claim 12, wherein a dimension of the first output transistor is smaller than a dimension of the second output transistor.

16. The semiconductor integrated circuit according to claim 5, wherein an ESD (Electrostatic Discharge) protection circuit is connected to an output line connecting the second node and the output terminal.

17. The semiconductor integrated circuit according to claim 12, wherein an ESD (Electrostatic Discharge) protection circuit is connected to an output line connecting the second node and the output terminal.

6. A semiconductor integrated circuit comprising:

an output circuit connected between a first node on an input terminal side and a second node on an output terminal side, circuit resistance between the first node and the second node being able to be switched;

an error amplifier that has a non-inverting input terminal, an inverting input terminal, and an output terminal, the non-inverting input terminal being connected to a third node between the second node and a standard potential, the inverting input terminal being connected to a reference voltage, and the output terminal being connected to the output circuit; and

a control circuit that makes circuit resistance of the output circuit at startup higher than circuit resistance of the output circuit at steady operation,

wherein the output circuit has;

an output transistor connected between the first node and the second node;

a first resistor connected in series to the output transistor between the first node and the second node; and

a first switch connecting opposite ends of the first resistor, and

wherein the control circuit compares the voltage on the output terminal and a threshold and controls the on/off of the first switch according to a comparison result.

7. The semiconductor integrated circuit according to claim 6, wherein if the voltage on the output terminal is less than or equal to the threshold, the control circuit controls the first switch to be off and, if the voltage on the output terminal exceeds the threshold, controls the first switch to be on.

8. The semiconductor integrated circuit according to claim 6, wherein the first resistor is a variable resistor.