Computer architecture having selectable, parallel and serial communication channels between processors and memory

• US 10,108,220 B2
• Filed: 05/01/2014
• Issued: 10/23/2018
• Est. Priority Date: 05/01/2014
• Status: Active Grant

• Current Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Original Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Inventors: Wang, Hao, Kim, Nam Sung
• Primary Examiner(s): Vo, Tim T
• Assistant Examiner(s): Dang, Phong H
• Application Number:
  US14/267,190
• Publication Number:
  US 20150317277A1
• Time in Patent Office: 1,636 Days
• Field of Search: 710 38, 710316
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 2213/0038 System on Chip
• CPC Class Codes: G06F 2213/0042 Universal serial bus [USB]
• CPC Class Codes: G06F 2213/0064 Latency reduction in handling transfers
• CPC Class Codes: G06F 3/0635 by changing the path, e.g. traffic rerouting, path reconfiguration

Abstract

A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.

Claims

1. An electronic computer comprising:

a processor system having;

(a) a first latency-sensitive processor executing a general instruction set for general purpose computation;

(b) a second latency-insensitive processor executing a specialized instruction set for specialized computation, wherein the latency-insensitive processor is less sensitive to latency in access to electronic memory than the latency-sensitive processor;

an electronic memory communicating with the processor system and storing data words for reading and writing by the processor system at memory addresses, the electronic memory including a first memory bank having a first address range and a second memory bank having a second address range different from the first address range;

a parallel bus communicating between the processor system and the first memory bank providing transmission of different bits of given data words in parallel on separate conductors of a parallel lane and not communicating with the second memory bank;

a serial bus communicating between the processor system and the second memory bank providing transmission of different bits of given data words serially on at least one conductor of a serial lane, and not communicating with the first memory bank; and

a memory access manager;

(a) providing communication between the electronic memory and the first latency-sensitive processor on both of the parallel bus and the serial bus;

(b) providing communication between the electronic memory and the second latency-insensitive processor on both of the parallel bus and the serial bus;

(c) dynamically selecting between the parallel bus and serial bus for communication between the electronic memory and each processor of the processor system as determined by a memory address of data being communicated falling within either of the first address range or second address range.

2. The electronic computer of claim 1 wherein the memory access manager identifies one of the parallel bus and serial bus for access of a given data word according to one of the processors first storing the given data word in the electronic memory.

3. The electronic computer of claim 1 the electronic memory including different memory banks exclusively accessible by one of the serial bus and parallel bus.

4. The electronic computer of claim 1 wherein the electronic memory allows access to data words according to address words and wherein the parallel bus provides transmission of multiple bits of each address word in parallel on separate conductors and the serial bus provides transmission of multiple bits of each address word in series on at least one conductor.

5. The electronic computer of claim 1 wherein the serial bus provides for multiple serial lanes and wherein each serial lane has an independent clock for synchronizing the serial transmission of different bits of given data words;

and

wherein the parallel lane has a single clock for synchronizing the parallel transmission of different bits on the separate conductors.

6. The electronic computer of claim 5 wherein the serial bus employs a self-clocking protocol for transmitting multiple bits of a digital word in series using a clock signal encoded in the transmission of the digital word and wherein the parallel bus employs a clock signal independent of digital words transmitted.

7. The electronic computer of claim 6 wherein the serial bus employs packet transmission in which multiple bits of words are transmitted in series as packets having header data and error correction data.

8. The electronic computer of claim 7 wherein the serial bus employs a low-voltage differential transmission on a conductor pair and wherein the parallel bus employs single-ended transmissions on a single conductor.

9. The electronic computer of claim 8 wherein the serial bus provides a bit rate on each conductor of at least 15 Gb per second.

10. The electronic computer of claim 1 wherein the serial bus has higher latency in communicating data words between the processor system and memory than the parallel bus.

11. The electronic computer of claim 1 wherein the latency-sensitive processor and latency-insensitive processor may both communicate with memory over either the serial bus or parallel bus.

12. The electronic computer of claim 1 wherein the memory access manager is implemented in part by software executed on the processor system.

13. The electronic computer of claim 1 wherein the latency-insensitive processor is a graphics processing unit and wherein the latency-sensitive processor is a general processing unit.

14. The electronic computer of claim 1 Wherein the latency-insensitive processor has at least 100 cores.

15. The electronic computer of claim 1 wherein the latency-insensitive processor is a specialized processor for streaming data selected from the group of video data and audio data.

16. The electronic computer of claim 1 wherein the latency-sensitive processor and latency-insensitive processor and at least a portion of the parallel bus and serial bus are integrated circuits integrated on a common substrate.