Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor

• US 10,108,417 B2
• Filed: 09/21/2015
• Issued: 10/23/2018
• Est. Priority Date: 08/14/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Krishna, Anil, Smith, Rodney Wayne, Navada, Sandeep Suresh, Priyadarshi, Shivam, Damodaran, Raguram
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US14/860,032
• Publication Number:
  US 20170046154A1
• Time in Patent Office: 1,128 Days
• Field of Search: None
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory

Abstract

Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor (OoP) is provided. An OoP is provided that includes an instruction processing system. The instruction processing system includes a number of instruction processing stages configured to pipeline the processing and execution of instructions according to a dataflow execution. The instruction processing system also includes a register map table (RMT) configured to store address pointers mapping logical registers to physical registers in a physical register file (PRF) for storing produced data for use by consumer instructions without overwriting logical registers for later executed, out-of-order instructions. In certain aspects, the instruction processing system is configured to write back (i.e., store) narrow values produced by executed instructions directly into the RMT, as opposed to writing the narrow produced values into the PRF in a write back stage.

Claims

1. An instruction processing system for a processor, comprising:

an in-order processing stage configured to fetch an instruction from an instruction memory; and

an out-of-order processing stage, comprising;

an execution circuit configured to execute the instruction; and

a writeback circuit configured to;

determine if a produced value generated for the executed instruction in the execution circuit is a narrow produced value; and

responsive to the produced value for the executed instruction being a narrow produced value, write back the narrow produced value as information to a mapping entry mapped to a logical register of a destination register operand of the executed instruction, of a register map table (RMT) comprising a plurality of mapping entries each configured to store at least one address pointer pointing to an address of a physical register in a physical register file (PRF);

wherein;

the in-order processing stage further comprises;

a register access (RACC) circuit configured to;

access a physical register in the physical register file (PRF) comprising a plurality of physical registers, based on a logical register of a source register operand of the instruction to retrieve a produced value from the executed instruction in the execution circuit; and

provide the retrieved produced value as the source register operand of the instruction; and

the out-of-order processing stage further comprises;

a dispatch circuit configured to;

dispatch the instruction from the RACC circuit to the execution circuit to be executed when all source register operands for the instruction are available.

2. The instruction processing system of claim 1, wherein the writeback circuit is further configured to, responsive to the produced value for the executed instruction being a wide produced value, write back the wide produced value to a physical register assigned to the destination register operand of the executed instruction in the physical register file (PRF).

3. The instruction processing system of claim 1, wherein, responsive to the produced value for the executed instruction being the narrow produced value, the writeback circuit is further configured to free an assigned physical register in the physical register file (PRF) to the destination register operand of the executed instruction.

4. The instruction processing system of claim 1, wherein the writeback circuit is further configured to determine from the register map table (RMT) if the destination register operand for the executed instruction is mapped to the physical register in the physical register file (PRF);

responsive to the destination register operand for the executed instruction being mapped to the mapping entry in the register map table (RMT), write back the narrow produced value to the mapping entry mapped to the destination register operand of the executed instruction, in the register map table (RMT).

5. The instruction processing system of claim 4, wherein the writeback circuit is configured to determine from the register map table (RMT) if the destination register operand for the executed instruction is mapped to the physical register in the physical register file (PRF) by being configured to:

access a filter table comprising a plurality of mapped indicators each corresponding to a physical register in the physical register file (PRF) indicating if the physical register is mapped;

a

responsive to a mapped indicator of the plurality of mapped indicators in the filter table indicating the physical register is mapped to the destination register operand of the executed instruction, write back the narrow produced value to the mapping entry mapped to the destination register operand of the executed instruction, in the register map table (RMT).

6. The instruction processing system of claim 5, wherein:

the in-order processing stage further comprises a rename circuit configured to;

receive the instruction;

access the register map table (RMT) to map the mapping entry based on the logical register of the destination register operand of the instruction to the physical register in the physical register file (PRF); and

clear the mapped indicator in the filter table corresponding to the physical register mapped to the destination register operand of the instruction.

7. The instruction processing system of claim 5, wherein the writeback circuit is further configured to, responsive to the mapped indicator in the filter table indicating that the physical register is not mapped to the destination register operand of the executed instruction, write back the narrow produced value to the mapping entry mapped to the destination register operand of the executed instruction, in a register map patch history table comprising a plurality of mapping entries each configured to store at least one address pointer to an address of a physical register in the physical register file (PRF).

8. The instruction processing system of claim 7, configured to recover the register map table (RMT) to a previous speculative state in response to a precise interrupt generated in the processor.

9. The instruction processing system of claim 1, wherein the writeback circuit is further configured to forward the produced value for the executed instruction via a data forwarding network to the dispatch circuit to be used as a source value for the source register operand of the instruction identified as not ready.

10. The instruction processing system of claim 9, wherein the RACC circuit is further configured to:

access a ready table to determine if the produced value for the source register operand of the instruction is ready to be consumed; and

responsive to determining that the produced value for the source register operand of the instruction is not ready to be consumed, dispatching the instruction to the dispatch circuit without the produced value for the source register operand of the instruction.

11. The instruction processing system of claim 1, wherein the writeback circuit is configured to determine if the produced value generated for the executed instruction in the execution circuit is the narrow produced value by being configured to determine a number of significant bits in the produced value.

12. The instruction processing system of claim 1 comprising the physical register file (PRF).

13. The instruction processing system of claim 12, wherein the out-of-order processing stage comprises a plurality of out-of-order instruction processing lanes, the out-of-order processing stage configured to process instructions in the plurality of out-of-order instruction processing lanes.

14. The instruction processing system of claim 13, further comprising the register map table (RMT) comprising the plurality of mapping entries each configured to store a number of the at least one address pointer less than a number of the plurality of out-of-order instruction processing lanes, pointing to an address of a physical register in the physical register file (PRF).

15. The instruction processing system of claim 14, wherein the register map table (RMT) contains fewer write ports than the number of the plurality of out-of-order instruction processing lanes.

16. The instruction processing system of claim 14, wherein a bit width of the narrow produced value is equal to a bit width of the at least one address pointer.

17. The instruction processing system of claim 13, wherein the in-order processing stage is configured to process the instructions in a plurality of in-order instruction processing lanes per clock cycle of the processor.

18. The instruction processing system of claim 1, wherein:

the in-order processing stage further comprises a rename circuit configured to;

receive the instruction;

read the register map table (RMT) at a mapping entry mapped to a logical register of the source register operand of the instruction to receive information stored in a physical register in the physical register file (PRF) based on the source register operand of the instruction;

determine if the received information from the register map table (RMT) is a narrow produced value or an address pointer mapped to a physical register in the physical register file (PRF) storing a wide produced value; and

responsive to the received information from the register map table (RMT) being the narrow produced value, provide the received information as the produced value for the source register operand of the instruction.

19. The instruction processing system of claim 15, wherein:

the in-order processing stage further comprises;

a register access (RACC) circuit configured to;

access a physical register in the physical register file (PRF) comprising a plurality of physical registers, based on a mapping entry mapped to a logical register of a source register operand of the instruction to retrieve a produced value from the executed instruction in the execution circuit; and

provide the retrieved produced value as the source register operand of the instruction; and

the RACC circuit is further configured to, responsive to the rename circuit receiving the address pointer from the register map table (RMT) being the wide produced value;

access the physical register at the address pointer in the physical register file (PRF) to retrieve the wide produced value stored in the physical register; and

provide the received wide produced value for the source register operand of the instruction.

20. The instruction processing system of claim 19, wherein, responsive to the rename circuit receiving the address pointer from the register map table (RMT) being the narrow produced value for a group of instructions, the rename circuit is further configured to bypass the RACC circuit to provide the group of instructions to a dispatch circuit.

21. The instruction processing system of claim 18, wherein the rename circuit is configured to read the register map table (RMT) at the mapping entry mapped to the logical register of the source register operand of the instruction to receive the information in the physical register in the physical register file (PRF) based on the source register operand of the instruction, by being configured to:

read a value register map table (RMT) at the mapping entry mapped to the logical register of the source register operand of the instruction to determine if a pointer register map table (RMT) or the value register map table (RMT) contains a valid data entry for the mapping entry mapped to the logical register of the source register operand of the instruction;

responsive to determining that the pointer register map table (RMT) contains a valid data entry for the mapping entry mapped to the logical register of the source register operand of the instruction, provide the received information at the mapping entry in the pointer register map table (RMT) as the narrow produced value for the source register operand of the instruction; and

responsive to determining that the value register map table (RMT) contains a valid data entry for the mapping entry mapped to the logical register of the source register operand of the instruction, access the physical register in the physical register file (PRF) at the address pointer of the information stored in the mapping entry in the value register map table (RMT) to retrieve a wide produced value stored in the physical register.

22. The instruction processing system of claim 1 integrated into a system-on-a-chip (SoC).

23. The instruction processing system of claim 1 integrated into a device selected from the group consisting of:

a set top box;

an entertainment unit;

a navigation device;

a communications device;

a fixed location data unit;

a mobile location data unit;

a mobile phone;

a cellular phone;

a computer;

a portable computer;

a desktop computer;

a personal digital assistant (PDA);

a monitor;

a computer monitor;

a television;

a tuner;

a radio;

a satellite radio;

a music player;

a digital music player;

a portable music player;

a digital video player;

a video player;

a digital video disc (DVD) player; and

a portable digital video player.

24. An instruction processing system for a processor, comprising:

a means for fetching an instruction from an instruction memory;

a means for executing the instruction;

a means for determining if a produced value generated for the executed instruction is a narrow produced value;

responsive to the produced value for the executed instruction being a narrow produced value, a means for writing back the narrow produced value as information to a mapping entry mapped to a logical register of a destination register operand of the executed instruction, of a register map table (RMT) comprising a plurality of mapping entries each configured to store at least one address pointer pointing to an address of a physical register in a physical register file (PRF);

a means for accessing a physical register in the physical register file (PRF) comprising a plurality of physical registers, based on a mapping entry mapped to a logical register of a source register operand of the instruction to retrieve a produced value from the executed instruction in an execution circuit in an out-of-order processing stage;

a means for providing the retrieved produced value as the source register operand of the instruction; and

a means for dispatching the instruction from an in-order processing stage to the execution circuit in the out-of-order processing stage to be executed when all source register operands for the instruction are available.

25. A method of processing an instruction in a processor, comprising:

fetching an instruction in an in-order processing stage from an instruction memory;

executing the instruction in an out-of-order processing stage;

determining if a produced value generated for the executed instruction is a narrow produced value; and

responsive to the produced value for the executed instruction being a narrow produced value, writing back the narrow produced value from the out-of-order processing stage as information to a mapping entry mapped to a logical register of a destination register operand of the executed instruction, of a register map table (RMT) comprising a plurality of mapping entries each configured to store at least one address pointer pointing to an address of a physical register in a physical register file (PRF);

accessing, in the in-order processing stage, a physical register in the physical register file (PRF) comprising a plurality of physical registers, based on a mapping entry mapped to a logical register of a source register operand of the instruction to retrieve a produced value from the executed instruction in an execution circuit in the out-of-order processing stage;

providing, in the in-order processing stage, the retrieved produced value as the source register operand of the instruction; and

dispatching the instruction from the in-order processing stage to the execution circuit in the out-of-order processing stage to be executed when all source register operands for the instruction are available.

26. The method of claim 25, further comprising, responsive to the produced value for the executed instruction being a wide produced value, writing back the wide produced value to the physical register assigned to the destination register operand of the executed instruction in the physical register file (PRF).

27. The method of claim 25, further configured to, responsive to the produced value for the executed instruction being the narrow produced value, freeing an assigned physical register in the physical register file (PRF) to the destination register operand of the executed instruction.

28. The method of claim 25, further comprising:

determining, from the register map table (RMT), if the destination register operand for the executed instruction is mapped to the physical register in the physical register file (PRF); and

responsive to the destination register operand for the executed instruction being mapped to the mapping entry in the register map table (RMT), writing back the narrow produced value to the mapping entry mapped to the logical register of the destination register operand of the executed instruction, in the register map table (RMT).

29. The method of claim 25, further comprising forwarding the produced value for the executed instruction via a forwarding path to be used as a source value for the source register operand of the instruction identified as not ready.

30. The method of claim 25, further comprising:

reading the register map table (RMT) at a mapping entry mapped to a logical register of a source register operand of the instruction in the in-order processing stage to receive information based on the source register operand of the instruction;

determining if the received information from the register map table (RMT) is a narrow produced value or an address pointer mapped to a physical register in the physical register file (PRF) storing a wide produced value; and

providing the received information as the produced value for the source register operand of the instruction if the received address pointer from the register map table (RMT) is a narrow produced value.