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Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor

  • US 10,108,417 B2
  • Filed: 09/21/2015
  • Issued: 10/23/2018
  • Est. Priority Date: 08/14/2015
  • Status: Active Grant
First Claim
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1. An instruction processing system for a processor, comprising:

  • an in-order processing stage configured to fetch an instruction from an instruction memory; and

    an out-of-order processing stage, comprising;

    an execution circuit configured to execute the instruction; and

    a writeback circuit configured to;

    determine if a produced value generated for the executed instruction in the execution circuit is a narrow produced value; and

    responsive to the produced value for the executed instruction being a narrow produced value, write back the narrow produced value as information to a mapping entry mapped to a logical register of a destination register operand of the executed instruction, of a register map table (RMT) comprising a plurality of mapping entries each configured to store at least one address pointer pointing to an address of a physical register in a physical register file (PRF);

    wherein;

    the in-order processing stage further comprises;

    a register access (RACC) circuit configured to;

    access a physical register in the physical register file (PRF) comprising a plurality of physical registers, based on a logical register of a source register operand of the instruction to retrieve a produced value from the executed instruction in the execution circuit; and

    provide the retrieved produced value as the source register operand of the instruction; and

    the out-of-order processing stage further comprises;

    a dispatch circuit configured to;

    dispatch the instruction from the RACC circuit to the execution circuit to be executed when all source register operands for the instruction are available.

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