Method and apparatus for waking a single core of a multi-core microprocessor, while maintaining most cores in a sleep state

• US 10,108,431 B2
• Filed: 09/14/2016
• Issued: 10/23/2018
• Est. Priority Date: 08/28/2013
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Henry, G. Glenn, Parks, Terry, Bean, Brent, Gaskins, Stephan
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US15/265,127
• Publication Number:
  US 20170003707A1
• Time in Patent Office: 769 Days
• Field of Search: 713300-340, 710260-269
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 2212/62 Details of cache specific to multiprocessor cache arrangements
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30105 Register structure
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/4418 Suspend and resume; Hibernate and awake
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Claims

1. A method for enabling most cores of a multi-core microprocessor to sleep while a designated one of the cores services non-directed wakeup events that are not directed to any specific core, the method comprising:

putting all of the cores to sleep and blocking wakeup events for all but a designated one of the cores, wherein said putting all of the cores to sleep comprises refraining from providing a clock signal and a power source to all of the cores;

in response to detecting a wakeup event, waking up the designated core to handle the detected wakeup event;

unblocking the wakeup events for the cores other than the designated core, regardless of whether there is any non-designated core to which a pending wakeup event is directed, so that in an event that a directed wakeup event is directed to a non-designated core, the non-designated core is enabled to respond to the directed wakeup event, and in an event that no directed wakeup event is directed to a non-designated event, all of the non-designated cores remain asleep;

putting the designated core back to sleep after the designated core services the wakeup event;

blocking wakeup events for all but the designated core;

keeping the other cores asleep, after said putting all of the cores to sleep, until a wakeup event is directed to one or more of the other cores.

2. The method of claim 1, further comprising appointing a last core to request to be put to sleep as the designated core.

3. The method of claim 1, wherein a control unit of the microprocessor performs the actions of putting all of the cores to sleep through keeping the other cores asleep.

4. The method of claim 1, wherein a control unit automatically performs said blocking wakeup events for all but one of the cores in response to detecting the designated core requested to be put to sleep after all the other cores requested to be put to sleep.

5. The method of claim 1, wherein a control unit performs said unblocking the wakeup events for the other cores than the designated core in response to the designated core requesting said unblocking.

6. The method of claim 1, wherein the actions of putting all of the cores to sleep and blocking wakeup events for all but the designated core follows, and is responsive to, each core executing an instruction that specifies a target power-saving idle state.

7. The method of claim 1, wherein the designated core writes a sync request that it be awakened only by de-assertion of STPCLK.

8. The method of claim 2, wherein when the designated core is the last core to write the sync request, a control unit automatically blocks off all wakeup events for the other cores.

9. The method of claim 2, further comprising:

waking up a second one of the cores other than the designated core when a pending directed wakeup event is directed to the second core;

the second core servicing the directed wakeup core;

the designated and second cores each requesting to be put to sleep;

appointing the second core as a newly designated core when the second core is the last core to request to be put to sleep, and un-appointing the formerly designated core as the designated core; and

repeating the actions of putting all of the cores to sleep through keeping the other cores asleep, until a wakeup event is directed to one or more of the other cores, wherein the other cores are defined in reference to the newly designated core.

10. The method of claim 7 wherein when a control unit detects the de-assertion of STPCLK, it wakes up the designated core and un-gates power to the designated core.

11. A multi-core microprocessor enabling most cores of a multi-core microprocessor to sleep while a designated one of the cores services non-directed wakeup events that are not directed to any specific core, the microprocessor characterized in that it is configured to:

put all of the cores to sleep and block wakeup events for all but a designated one of the cores, wherein said putting all of the cores to sleep comprises refraining from providing a clock signal and a power source to all of the cores;

in response to detecting a wakeup event, wake up the designated core to handle the detected wakeup event;

unblock the wakeup events for the cores other than the designated core, regardless of whether there is any non-designated core to which a pending wakeup event is directed, so that in an event that a directed wakeup event is directed to a non-designated core, the non-designated core is enabled to respond to the directed wakeup event, and in an event that no directed wakeup event is directed to a non-designated event, all of the non-designated cores remain asleep;

put the designated core back to sleep after the designated core services the wakeup event;

block wakeup events for all but the designated core;

keep the other cores asleep, after said putting all of the cores to sleep, until a wakeup event is directed to one or more of the other cores.

12. The microprocessor of claim 11, wherein the microprocessor is configured to appoint a last core to request to be put to sleep as the designated core.

13. The microprocessor of claim 11, wherein a control unit of the microprocessor is configured to perform the actions of putting all of the cores to sleep through keeping the other cores asleep.

14. The microprocessor of claim 11, wherein a control unit is configured to automatically perform said blocking wakeup events for all but one of the cores in response to detecting the designated core requested to be put to sleep after all the other cores requested to be put to sleep.

15. The microprocessor of claim 11, wherein a control unit is configured to perform said unblocking the wakeup events for the other cores than the designated core in response to the designated core requesting said unblocking.

16. The microprocessor of claim 11, wherein the actions of putting all of the cores to sleep and blocking wakeup events for all but the designated core follows, and is responsive to, each core executing an instruction that specifies a target power-saving idle state.

17. The microprocessor of claim 11, wherein the designated core is configured to write a sync request that it be awakened only by de-assertion of STPCLK.

18. The microprocessor of claim 12, wherein when the designated core is the last core to write the sync request, a control unit is configured to automatically blocks off all wakeup events for the other cores.

19. The microprocessor of claim 12, further characterized in that the microprocessor is configured to:

wake up a second one of the cores other than the designated core when a pending directed wakeup event is directed to the second core;

have the second core service the directed wakeup core;

have the designated and second cores each request to be put to sleep;

appoint the second core as a newly designated core when the second core is the last core to request to be put to sleep, and un-appointing the formerly designated core as the designated core; and

repeat the actions of putting all of the cores to sleep through keeping the other cores asleep, until a wakeup event is directed to one or more of the other cores, wherein the other cores are defined in reference to the newly designated core.

20. The microprocessor of claim 17 wherein when a control unit is configured to detect the de-assertion of STPCLK, it wakes up the designated core and un-gates power to the designated core.