Averting lock contention associated with core-based hardware threading in a split core environment

• US 10,108,453 B2
• Filed: 06/30/2016
• Issued: 10/23/2018
• Est. Priority Date: 06/30/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Accapadi, Mathew, Davidson, II, Grover C., Michel, Dirk, Olszewski, Bret R.
• Primary Examiner(s): Nguyen, Van
• Application Number:
  US15/199,258
• Publication Number:
  US 20180004571A1
• Time in Patent Office: 845 Days
• Field of Search: None
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3055 Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available error or fault processing without redundancy G06F11/0703; error detection or correction by redundancy in data representation G06F11/08; error detection or correction by redundancy in operation G06F11/14; error detection or correction by redundancy in hardware G06F11/16
• CPC Class Codes: G06F 9/4887 involving deadlines, e.g. rate based, periodic
• CPC Class Codes: G06F 9/524 Deadlock detection or avoidance

Abstract

Techniques are disclosed for managing lock contention in a multithreaded processing system. In one embodiment, a method includes tracking a current total amount of time that one or more software threads are prevented from execution due to a lock, a current utilization of one or more hardware threads in the processor, and a current number of dispatchable software threads. If the current total amount of time exceeds a predetermined threshold, the method includes performing a comparison of the current total amount of time, the current utilization, and the current number of dispatchable software threads to one or more past measurements. Based on the comparison, the method includes determining if reducing a number of active hardware threads will reduce a wait time. If reducing the number of active hardware threads will reduce the wait time, reducing the number of active hardware threads.

Claims

1. A method for managing lock contention in a processor, comprising:

tracking, in a table stored in a memory, a current total amount of time that one or more software threads are prevented from execution due to a lock;

tracking, in the table, a current utilization of one or more hardware threads in the processor, wherein each of the hardware threads form an execution stream on a processor core;

tracking, in the table, a current number of software threads that are dispatched to the hardware threads for execution on the processor core;

if the current total amount of time exceeds a predetermined threshold, performing a comparison of the current total amount of time, the current utilization, and the current number of software threads to one or more past measurements;

based on the comparison, predicting that reducing a number of active hardware threads will reduce a wait time by;

determining that the one or more past measurements comprise a smaller number of active hardware threads compared to a current number of active hardware threads; and

determining that the one or more past measurements associated with the smaller number of active hardware threads comprise a reduced wait time for software threads compared to the current total amount of time; and

if reducing the number of active hardware threads will reduce the wait time, reducing the number of active hardware threads.

2. The method of claim 1, wherein reducing the number of active hardware threads comprises reducing the number of active hardware threads for a predetermined number of processing cycles.

3. The method of claim 2, further comprising, after the predetermined number of processing cycles:

increasing the number of active hardware threads; and

tracking the current total amount of time that one or more software threads are prevented from execution due to a lock.

4. The method of claim 1, wherein performing the comparison comprises comparing the current utilization and the current number of software threads to one or more past measurements that are similar to the current measurements.

5. The method of claim 1, wherein a current total amount of time is tracked utilizing one or more hint bits in an instruction set.

6. The method of claim 5, wherein a first hint bit in a first instruction denotes a beginning of a lock operation, and a second hint bit in a second instruction denotes an end of the lock operation.

7. The method of claim 1, wherein the one or more software threads that are prevented from execution enter a low-priority spinning mode.

8. A computer program product for managing lock contention, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code embodied therewith, the computer-readable program code executable by a processor to cause the processor to:

track, in a table stored in a memory, a current total amount of time that one or more software threads are prevented from execution due to a lock;

track, in the table, a current utilization of one or more hardware threads in the processor, wherein each of the hardware threads form an execution stream on a processor core;

track, in the table, a current number of software threads that are dispatched to the hardware threads for execution on the processor core;

if the current total amount of time exceeds a predetermined threshold, perform a comparison of the current total amount of time, the current utilization, and the current number of software threads to one or more past measurements;

based on the comparison, predict that reducing a number of active hardware threads will reduce a wait time by;

determining that the one or more past measurements comprise a smaller number of active hardware threads compared to a current number of active hardware threads; and

determining that the one or more past measurements associated with the smaller number of active hardware threads comprise a reduced wait time for software threads compared to the current total amount of time; and

if reducing the number of active hardware threads will reduce the wait time, reduce the number of active hardware threads.

9. The computer program product of claim 8, wherein the computer-readable program code further causes the processor to:

reduce the number of active hardware threads for a predetermined number of processing cycles.

10. The computer program product of claim 9, wherein the computer-readable program code further causes the processor to, after the predetermined number of processing cycles:

increase the number of active hardware threads; and

track the current total amount of time that one or more software threads are prevented from execution due to a lock.

11. The computer program product of claim 8, wherein performing the comparison comprises comparing the current utilization and the current number of software threads to one or more past measurements that are similar to the current measurements.

12. The computer program product of claim 8, wherein the computer-readable program code tracks a current total amount of time utilizing one or more hint bits in an instruction set.

13. The computer program product of claim 12, wherein a first hint bit in a first instruction denotes a beginning of a lock operation, and a second hint bit in a second instruction denotes an end of the lock operation.

14. The computer program product of claim 8, wherein the one or more software threads that are prevented from execution enter a low-priority spinning mode.

15. A system, comprising:

a processor; and

a memory storing a program, which, when executed on the processor, performs an operation for managing lock contention, the operation comprising;

tracking, in a table stored in a memory, a current total amount of time that one or more software threads are prevented from execution due to a lock;

tracking, in the table, a current utilization of one or more hardware threads in the processor, wherein each of the hardware threads form an execution stream on a processor core;

tracking, in the table, a current number of software threads that are dispatched to the hardware threads for execution on the processor core;

if the current total amount of time exceeds a predetermined threshold, performing a comparison of the current total amount of time, the current utilization, and the current number of software threads to one or more past measurements;

based on the comparison, predicting that reducing a number of active hardware threads will reduce a wait time by;

determining that the one or more past measurements comprise a smaller number of active hardware threads compared to a current number of active hardware threads; and

determining that the one or more past measurements associated with the smaller number of active hardware threads comprise a reduced wait time for software threads compared to the current total amount of time; and

if reducing the number of active hardware threads will reduce the wait time, reducing the number of active hardware threads.

16. The system of claim 15, wherein reducing the number of active hardware threads comprises reducing the number of active hardware threads for a predetermined number of processing cycles.

17. The system of claim 16, the operations further comprising, after the predetermined number of processing cycles:

increasing the number of active hardware threads; and

tracking the current total amount of time that one or more software threads are prevented from execution due to a lock.

18. The system of claim 15, wherein performing the comparison comprises comparing the current utilization and the current number of software threads to one or more past measurements that are similar to the current measurements.

19. The system of claim 15, wherein a current total amount of time is tracked utilizing one or more hint bits in an instruction set.

20. The system of claim 19, wherein a first hint bit in a first instruction denotes a beginning of a lock operation, and a second hint bit in a second instruction denotes an end of the lock operation.