Memory cells, memory cell arrays, methods of using and methods of making

• US 10,109,349 B2
• Filed: 04/09/2018
• Issued: 10/23/2018
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductors, Inc.
• Inventors: Widjaja, Yuniarto
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/948,926
• Publication Number:
  US 20180233199A1
• Time in Patent Office: 197 Days
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 14/0045 and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 43/30 : characterised by the memory core region
• CPC Class Codes: H10B 63/00 : Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10N 70/231 : based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/8828 : Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/883 : Oxides or nitrides

Abstract

A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

Claims

1. An integrated circuit comprising:

a semiconductor memory array comprising;

a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include;

a transistor comprising a source region, a first floating body region, a drain region, and a gate; and

a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region;

a non-volatile memory comprising a resistance change element configured to store data stored in said first floating body region upon transfer thereto; and

a control circuit configured to perform said transfer;

wherein a state of said memory cell is stored in said first floating body region when power is applied to said cell;

wherein said first floating body region and said second floating body region are common;

wherein said silicon controlled rectifier device maintains a state of said memory cell;

wherein said transistor is usable to access said memory cell; and

wherein said transfer is performable to said at least two of said memory cells in parallel.

2. The integrated circuit of claim 1, wherein said resistance change element comprises a phase change material.

3. The integrated circuit of claim 1, wherein said resistance change element comprises a metal-oxide-metal system.

4. The integrated circuit of claim 1, wherein said non-volatile memory is configured to store said data stored in said floating body upon receiving an instruction to back up said data stored in said floating body.

5. The integrated circuit of claim 1, wherein said non-volatile memory is configured to store said data stored in said first floating body region upon a loss of power to said array, wherein said array is configured to perform a shadowing process wherein said data in said first floating body region is loaded into and stored in said non-volatile memory.

6. The integrated circuit of claim 5, wherein said loss of power to said array is one of unintentional power loss or intentional power loss, wherein said intentional power loss is predetermined to conserve power.

7. The integrated circuit of claim 5, wherein, upon restoration of power to said array, said data in said non-volatile memory is loaded into said first floating body region and stored therein.

8. The integrated circuit of claim 7, wherein said array is configured to reset said non-volatile memory to an initial state after loading said data into said first floating body region upon said restoration of power.

9. An integrated circuit comprising:

a semiconductor memory array comprising;

a plurality of memory cells arranged in a matrix of rows and columns, wherein at least two of said memory cells each include;

a transistor comprising a source region, a first floating body region, a drain region, and a gate, and

a silicon controlled rectifier device having a cathode region, a second floating body region, a buried layer region, and an anode region;

a nonvolatile memory comprising a resistance change element configured to store data stored in said first floating body region upon transfer thereto;

a first control circuit configured to provide electrical signals to said transistor to access said memory cell; and

a second control circuit configured to perform said transfer;

wherein a state of said memory cell is stored in said first floating body region when power is applied to said cell;

wherein said first floating body region and said second floating body region are common;

wherein said silicon controlled rectifier device maintains a state of said memory cell;

wherein said transistor is usable to access said memory cell;

wherein said anode region is commonly connected to at least two of said memory cells; and

wherein said transfer is performable to said at least two of said memory cells in parallel.

10. The integrated circuit of claim 9, wherein said resistance change element comprises a phase change material.

11. The integrated circuit of claim 9, wherein said resistance change element comprises a metal-oxide-metal system.

12. The integrated circuit of claim 9, wherein said non-volatile memory is configured to store said data stored in said silicon controlled rectifier device upon receiving an instruction to back up said data stored in said silicon controlled rectifier device.

13. The integrated circuit of claim 9, wherein said non-volatile memory is configured to store said data stored in said silicon controlled rectifier device upon a loss of power to said cell, wherein said cell is configured to perform a shadowing process wherein said data in said silicon controlled rectifier device is loaded into and stored in said non-volatile memory.

14. The integrated circuit of claim 13, wherein said loss of power to said cell is one of unintentional power loss or intentional power loss, wherein said intentional power loss is predetermined to conserve power.

15. The integrated circuit of claim 13, wherein, upon restoration of power to said cell, said data in said non-volatile memory is loaded into said silicon controlled rectifier device and stored therein.

16. The integrated circuit of claim 15, wherein said cell is configured to reset said non-volatile memory to an initial state after loading said data into said silicon controlled rectifier device upon said restoration of power.

17. The integrated circuit of claim 9, wherein said silicon controlled rectifier device is formed in a fin.

18. The integrated circuit of claim 9, wherein said data stored in said silicon controlled rectifier device determines a current flowing to said non-volatile memory.