Fabrication of sacrificial interposer test structure

• US 10,109,540 B2
• Filed: 06/08/2016
• Issued: 10/23/2018
• Est. Priority Date: 06/08/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mori, Hiroyuki, Okamoto, Keishi
• Primary Examiner(s): Gheyas, Syed
• Application Number:
  US15/176,935
• Publication Number:
  US 20170358507A1
• Time in Patent Office: 867 Days
• CPC Class Codes: G01R 31/2637 for testing other individual devices G01R31/2608 - G01R31/2632, G01R31/27 take precedence
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/44 Testing lamps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout

Abstract

A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface, and a tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.

Claims

1. A sacrificial interposer test structure, comprising:

a release layer;

a dummy layer on the release layer;

one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface; and

a conductive tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.

2. The sacrificial interposer test structure of claim 1, wherein the dummy layer is formed of a photoresist resin, and the one or more conductive pads are copper.

3. The sacrificial interposer test structure of claim 1, wherein the conductive tie layer comprises a layer of titanium and a layer of copper on the layer of titanium.

4. The sacrificial interposer test structure of claim 1, further comprising a substitute, wherein the release layer is on the substrate, and provides an interface that allows the substrate to be separated from the dummy layer, one or more conductive pads, and conductive tie layer.

5. The sacrificial interposer test structure of claim 4, wherein the release layer is formed of a material that debonds from the substrate surface subsequent to the interface of the release layer with the substrate being exposed to a laser.

6. The sacrificial interposer test structure of claim 5, wherein the release layer comprises titanium.

7. The sacrificial interposer test structure of claim 1, further comprising an interposer formed on the conductive tie layer, where the interposer comprises an interposer body, one or more interposer via contacts, and two or more interposer lead contacts embedded in the interposer body, wherein each of the one or more interposer via contacts and two or more interposer lead contacts has a surface, and a plurality of the one or more interposer via contact surfaces and/or two or more interposer lead contact surfaces is in electrical contact with at least one of the one or more conductive pads.

8. The sacrificial interposer test structure of claim 7, further comprising one or more interposer chip contacts and one or more interposer leads embedded in the interposer body, wherein at least one of the one or more interposer leads formed an electrical connection between two or more interposer lead contacts, and at least two interposer chip contacts are electrically connected through least one of the one or more conductive pads.

9. A method of fabricating a sacrificial interposer test structure, comprising:

forming a release layer on a substrate;

forming a dummy layer on the release layer;

patterning and developing the dummy layer to form one or more recesses in the dummy layer;

forming conductive pads in the one or more recesses in the dummy layer, wherein each of the one or more conductive pads has an exposed surface; and

forming a conductive tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.

10. The method of claim 9, wherein the release layer is formed by depositing titanium on the substrate, and the dummy layer is formed of a photoresist resin.

11. The method of claim 9, which further comprises forming a photosensitive dry film on at least a portion of the conductive tie layer;

patterning and developing the photosensitive dry film to form one or more cavities in the photosensitive dry film; and

forming one or more interposer via contacts and/or one or more interposer lead contacts in the one or more cavities.

12. The method of claim 11, which further comprises removing the photosensitive dry film, and forming an insulator material on the exposed surfaces of the conductive tie layer, and that fills the space between the one or more interposer via contacts, and/or one or more interposer lead contacts.

13. The method of claim 12, which further comprises forming vias, leads, and interposer leads in the insulator material.

14. The method of claim 9, wherein the conductive tie layer comprises a layer of titanium and a layer of copper on the layer of titanium.

15. A method of testing an interposer, comprising:

forming a sacrificial test structure, wherein the sacrificial test structure includes a conductive tie layer and one or more conductive pads in contact with the conductive tie layer;

forming an interposer on the sacrificial test structure, wherein the interposer includes a body and a plurality of electrically connected interposer contacts and chip contacts embedded in the body, where at least a portion of the electrically connected interposer contacts are in electrical contact with the conductive tie layer of the sacrificial test structure; and

attaching at least two test probes to at least two different chip contacts on the surface of the interposer, wherein a resistance between the electrically connected interposer contacts is measured to determine if a conductive path between the electrically connected interposer contacts is open or closed.

16. The method of claim 15, wherein each of the one or more conductive pads forms a conductive bridge between two or more interposer contacts, such that a resistance for a complete conductive path between two chip contacts may be measured.

17. The method of claim 16, wherein the sacrificial test structure includes a release layer, and a substrate in contact with the release layer, wherein the release layer couples the conductive tie layer to the substrate.

18. The method of claim 17, wherein the interposer is discarded if the resistance for the complete conductive path between two chip contacts indicates the interposer is defective.

19. The method of claim 17, further comprising coupling the interposer to a handling structure, and separating the substrate from the sacrificial test structure at the release layer after measuring the resistance for the complete conductive path between two chip contacts.

20. The method of claim 19, wherein the release layer is titanium, and the substrate is separated from the sacrificial test structure by exposing the release layer to laser light.