Semiconductor device interconnect structures formed by metal reflow process

• US 10,109,586 B2
• Filed: 05/11/2017
• Issued: 10/23/2018
• Est. Priority Date: 12/14/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Murray, Conal E., Yang, Chih-Chao
• Primary Examiner(s): Nguyen, Thanh T
• Application Number:
  US15/592,291
• Publication Number:
  US 20170243830A1
• Time in Patent Office: 530 Days
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76882 Reflowing or applying of pressure to better fill the contact hole
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers

Abstract

Methods are devices are provided in which interconnection structures are formed using metal reflow techniques. For example, a method to fabricate a semiconductor device includes forming an opening in an ILD (inter-level dielectric) layer. The opening includes a via hole and a trench. A layer of diffusion barrier material is deposited to cover the ILD layer and to line the opening with the diffusion barrier material. A layer of first metallic material is deposited on the layer of diffusion barrier material to cover the ILD layer and to line the opening with the first metallic material. A reflow process is performed to allow the layer of first metallic material to reflow into the opening and at least partially fill the via hole with the first metallic material. A layer of second metallic material is deposited to at least partially fill a remaining portion of the opening in the ILD layer.

Claims

1. A semiconductor device, comprising:

an ILD (inter-level dielectric) layer comprising an opening, wherein the ILD layer is formed as part of a BEOL (back-end-of-line) structure and further wherein the opening comprises a via hole and a trench having sidewalls which is disposed over the via hole;

wherein the opening is lined with a layer of diffusion barrier material;

wherein the opening comprises a first metallic material that is disposed at a bottom of the via hole and which at least partially fills the via hole and lines the sidewalls of the trench, wherein the first metallic material comprises reflowed Cobalt; and

wherein the opening comprises a second metallic material that is in physical contact with the first metallic material and fills a remaining portion of the opening of the ILD layer, wherein the second metallic material is different than the first metallic material; and

wherein the second metallic material is in physical contact with the reflowed Cobalt.

2. The semiconductor device of claim 1, wherein the second metallic material comprises copper.

3. The semiconductor device of claim 1, wherein the second metallic material comprises a reflowed metallic material.

4. The semiconductor device of claim 1, wherein the second metallic material comprises W or Al.

5. The semiconductor device of claim 1, further comprising a seed layer disposed between the first metallic material and the second metallic material.

6. A semiconductor device, comprising:

an ILD (inter-level dielectric) layer comprising a metallic interconnect structure disposed within an opening etched into the ILD layer, wherein the ILD layer is formed as part of a BEOL (back-end-of-line) structure and further wherein the opening comprises a via hole and a trench which is disposed over the via hole;

wherein the metallic interconnect structure comprises a conductive via formed in the via hole and a metal line formed in the trench, which is disposed over the conductive via;

wherein the conductive via comprises a first metallic material, wherein the first metallic material comprises reflowed Cobalt which is disposed at a bottom of the via hole and which completely fills the via hole; and

wherein the metal line comprises a second metallic material which fills the trench and which is formed in physical contact with the reflowed Cobalt of the conductive via, wherein the second metallic material is different than the first metallic material.

7. The semiconductor device of claim 6, wherein the second metallic material comprises copper.

8. The semiconductor device of claim 6, wherein the second metallic material comprises W or Al.

9. The semiconductor device of claim 6, wherein the second metallic material comprises a reflowed metal material.

10. The semiconductor device of claim 6, wherein the metallic interconnect structure comprises a seed layer disposed between the the first metallic material and the second metallic material.

11. The semiconductor device of claim 10, wherein the metallic interconnect structure comprises a liner layer which is disposed between the ILD layer and the metal line, and between the ILD layer and an upper portion of the conductive via, wherein the liner layer is formed by the reflowed Cobalt.