Low-capacitance electrostatic damage protection device and method of designing and making same

• US 10,109,621 B2
• Filed: 02/09/2017
• Issued: 10/23/2018
• Est. Priority Date: 08/08/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Jam-Wem
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Fox, Brandon
• Application Number:
  US15/428,631
• Publication Number:
  US 20180040602A1
• Time in Patent Office: 621 Days
• Field of Search: 257173, 257328, 257355
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0262 including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence

Abstract

An electrostatic discharge (ESD) device includes an active region. The active region includes a first active line having a first plurality of gate features; and a second active line having a second plurality of gate features. The ESD device further includes a first pick-up line having a third plurality of gate features, wherein the first active line is between the first pick-up line and the second active line. The ESD device further includes a second pick-up line comprising a fourth plurality of gate features, wherein the second active line is between the second pick-up line and the first active line.

Claims

1. An electrostatic discharge (ESD) device comprising:

an active region, wherein the active region comprises;

a first active line comprising a first plurality of gate features; and

a second active line comprising a second plurality of gate features;

a first pick-up line comprising a third plurality of gate features, wherein the first active line is between the first pick-up line and the second active line; and

a second pick-up line comprising a fourth plurality of gate features, wherein the second active line is between the second pick-up line and the first active line.

2. The ESD device of claim 1, wherein a spacing between the first active line and the second active line is greater than a spacing between any two adjacent gate features of the first plurality of gate features.

3. The ESD device of claim 1, wherein a spacing between the first active line and the first pick-up line is greater than a spacing between any two adjacent gate features of the third plurality of gate features.

4. The ESD device of claim 1, further comprising a well in the substrate, wherein the well has a first dopant type.

5. The ESD device of claim 4, wherein the first active line comprises:

an upper region having a second dopant type, wherein the second dopant type is opposite the first dopant type; and

a lower region having the first dopant type, wherein the lower region is between the upper region and the well.

6. The ESD device of claim 4, wherein the first pick-up line comprises:

an upper region having the first dopant type, wherein a dopant concentration of the upper region is greater than a dopant concentration of the well; and

a lower region having the first dopant type, wherein the lower region is between the upper region and the well.

7. The ESD device of claim 1, further comprising:

a first isolation feature between the first active line and the second active line; and

a second isolation feature between the first active line and the first pick-up line.

8. The ESD device of claim 7, wherein the first isolation feature is continuous with the second isolation feature.

9. The ESD device of claim 7, wherein the first isolation feature is different from the second isolation feature.

10. The ESD device of claim 1, further comprising a third pick-up line, wherein the first pick-up line is between the third pick-up line and the first active line, and the third pick-up line comprises a plurality of gate features.

11. An electrostatic discharge (ESD) device comprising:

a well in a substrate, wherein the well has a first dopant type;

an active region over the well, wherein the active region comprises;

a first active line comprising a first plurality of gate features, wherein the first active line comprises an upper region having a second dopant type opposite the first dopant type; and

a second active line comprising a second plurality of gate features;

a first pick-up line over the well, wherein the first pick-up line comprises a third plurality of gate features, the first active line is between the first pick-up line and the second active line, and the first pick-up line comprises an upper region having the first dopant type; and

a second pick-up line over the well, wherein the second pick-up line comprises a fourth plurality of gate features, and the second active line is between the second pick-up line and the first active line,

wherein the ESD device has a dissipation path extending from the upper region of the first active line through the well to the upper region of the first pick-up line.

12. The ESD device of claim 11, wherein the first dopant type is a p-type dopant.

13. The ESD device of claim 11, further comprising:

a first isolation structure between the first active line and the second active line; and

a second isolation structure between the first active line and the first pick-up line.

14. The ESD device of claim 13, wherein a width of the first isolation structure is less than a width of the second isolation structure.

15. The ESD device of claim 13, wherein a width of the second isolation structure is less than a width of a third isolation structure, wherein the third isolation structure is between the second active line and the second pick-up line.

16. The ESD device of claim 11, further comprising a third active line between the first pick-up line and the second pick-up line, wherein the third active line comprises a fifth plurality of gate features.

17. The ESD device of claim 16, wherein the third active line is adjacent to the second active line, and a space between the third active line and the second active line is free of pick-up lines.

18. An integrated circuit layout generating system, comprising:

a non-transitory storage medium for storing a set of instructions; and

a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute the set of instructions, the set of instructions being configured to cause the processor to;

receive a design of an integrated circuit (IC);

decouple front-end components of the IC from back-end components of the IC;

determine a layout of the back-end components of the IC;

place the front-end components of the IC based on the layout of the back-end components;

perform a post-layout simulation based on the layout of the back-end components and the placed front-end components; and

adjust the layout of the back-end components in response to a determination that the post-layout simulation fails to satisfy design requirements of the IC.

19. The integrated circuit layout generating system of claim 18, wherein the hardware processor configured to execute the set of instructions, the set of instructions being further configured to cause the processor to:

generate instructions for forming at least one mask based on the layout of the back-end components and the placed front-end components in response to a determination that the post-layout simulation satisfies the design requirements of the IC.

20. The integrated circuit layout generating system of claim 18, wherein adjusting the layout of the back-end components comprises automatically proposing modifications to the layout of the back-end components in response to the determination that the post-layout simulation fails to satisfy the design requirements of the IC.