Semiconductor device and method of forming the same

• US 10,109,630 B2
• Filed: 05/24/2017
• Issued: 10/23/2018
• Est. Priority Date: 03/19/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Gan, Tian Choy, Hsiao, Chu-Yun, Hsu, Chia-Fu
• Primary Examiner(s): Hossain, Moazzam
• Assistant Examiner(s): Tynes, Jr., Lawrence
• Application Number:
  US15/604,638
• Publication Number:
  US 20170263608A1
• Time in Patent Office: 517 Days
• Field of Search: 257369, 438217, 438275
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.

Claims

1. A semiconductor device, comprising:

a substrate;

a first gate structure disposed in a first transistor region on the substrate, the first gate structure comprising;

a first channel, wherein the first channel comprises different dopant from that of adjacent doped regions and adjacent well region; and

a first work function layer; and

a second gate structure disposed in a second transistor region on the substrate, wherein the first transistor region and the second transistor region are same conductive type, the second gate structure comprising;

a second channel, wherein the second channel comprises different dopant from that of adjacent doped regions and adjacent well region, and the second channel comprises different dopants from that of the first channel; and

a second work function layer, wherein the second work function layer and the first work function layer have a same conductive type and different thicknesses.

2. The semiconductor device according to claim 1, wherein the first work function layer and the second work function layer comprise different materials.

3. The semiconductor device according to claim 1, further comprising:

a third gate structure disposed in a third transistor region on the substrate, wherein the third gate structure comprises;

a third channel, wherein the third channel comprises different dopant from that of adjacent doped regions and adjacent well region, and the third channel comprises different dopants from that of the first channel and the second channel; and

a third work function layer, having a conductive type different from that of the first work function layer and the second work function layer.

4. The semiconductor device according to claim 1, wherein the second channel layer and the first channel layer comprise different dopant dosages, and the adjacent doped region has a relatively lower dopant concentration, the first channel has highest dopant concentration, and the second channel has a relatively higher dopant concentration, respectively.

5. The semiconductor device according to claim 1, wherein the second channel layer and the first channel layer comprise different dopant materials.