Double-masking technique for increasing fabrication yield in superconducting electronics
First Claim
1. An integrated circuit based on a plurality of Nb-based Josephson junctions, comprising:
- a Josephson junction trilayer comprising a lower Nb-containing superconductive layer, an insulating layer, an upper Nb-containing superconductive layer, and sidewalls thereof, on a substrate, fabricated into at least one Josephson junction having a defined junction area less than 1 square micron, the at least one Josephson junction comprising an anodized double oxide layer of AlOx on top of NbOx, wherein the double oxide is patterned in a vacuum processing chamber using a dry etch process to provide a structure surrounding the defined junction comprising a continuous NbOx layer which extends vertically along the sidewalls of the lower Nb-containing superconductive layer, the insulating layer, and the upper Nb-containing superconductive layer; and
a silicon dioxide layer formed directly on top of the upper Nb-containing superconductor layer.
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Accused Products
Abstract
An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.
918 Citations
20 Claims
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1. An integrated circuit based on a plurality of Nb-based Josephson junctions, comprising:
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a Josephson junction trilayer comprising a lower Nb-containing superconductive layer, an insulating layer, an upper Nb-containing superconductive layer, and sidewalls thereof, on a substrate, fabricated into at least one Josephson junction having a defined junction area less than 1 square micron, the at least one Josephson junction comprising an anodized double oxide layer of AlOx on top of NbOx, wherein the double oxide is patterned in a vacuum processing chamber using a dry etch process to provide a structure surrounding the defined junction comprising a continuous NbOx layer which extends vertically along the sidewalls of the lower Nb-containing superconductive layer, the insulating layer, and the upper Nb-containing superconductive layer; and a silicon dioxide layer formed directly on top of the upper Nb-containing superconductor layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A Josephson junction integrated circuit, produced by a process comprising:
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depositing a Josephson junction trilayer comprising a lower superconductor layer, an insulating layer, and an upper superconductor layer, on a substrate; depositing a silicon dioxide layer directly on top of the upper superconductor layer by plasma-enhanced chemical vapor deposition (PECVD); depositing a photoresist having an adhesion to the silicon dioxide greater than a respective adhesion of the photoresist to the upper superconductor layer; patterning the photoresist; etching through the silicon dioxide layer and the upper superconductor layer to expose the insulating layer; anodizing exposed portions of the insulating layer and a portion of the lower superconductor layer, to thereby increase a layer thickness of the anodized insulating layer and the portion of the lower superconductor layer, with respect to the insulating layer and the portion of the lower superconductor layer, to create a continuous anodized portion of the lower superconductor layer which surrounds and extends vertically along sidewalls of the lower superconductor layer, the insulating layer, and the upper superconductor layer, and which interrupts the anodized insulating layer; and dry etching the anodized insulating layer and the portion of the lower superconductor layer, to produce a Josephson junction device. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A method of forming a Josephson junction integrated circuit, comprising:
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depositing a Josephson junction trilayer comprising a lower superconductor layer, an insulating layer, and an upper superconductor layer, on a substrate; depositing a silicon dioxide layer directly on top of the upper superconductor layer by plasma-enhanced chemical vapor deposition (PECVD); depositing a photoresist having an adhesion to the silicon dioxide greater than a respective adhesion of the photoresist to the upper superconductor layer;
patterning the photoresist;etching through the silicon dioxide layer and the upper superconductor layer to expose the insulating layer; anodizing exposed portions of the insulating layer and a portion of the lower superconductor layer, creating a continuous anodized portion of the lower superconductor layer surrounding and extending vertically along sidewalls of the lower superconductor layer, the insulating layer, and the upper superconductor layer of a defined junction and causing a discontinuity of the anodized insulating layer between the insulating layer and the anodized insulating layer; and dry etching the anodized insulating layer and the portion of the lower superconductor layer, to produce a Josephson junction device. - View Dependent Claims (19, 20)
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Specification