Semiconductor device and manufacturing method thereof

• US 10,109,720 B1
• Filed: 06/09/2017
• Issued: 10/23/2018
• Est. Priority Date: 04/24/2017
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Yin, Tan-Ya, Huang, Chia-Wei
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US15/618,141
• Publication Number:
  US 20180308954A1
• Time in Patent Office: 501 Days
• Field of Search: 438156, 438173, 438192, 438212, 438268
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a patterned conductive layer and an epitaxial layer. The substrate includes a first fin structure and a second fin structure respectively protruding from a top surface of the substrate, and the second fin structure has a recess. The patterned conductive layer is disposed on the substrate and covers a first end of the first fin structure. The epitaxial layer is disposed in the recess. The first end of the first fin structure and a second end of the epitaxial layer face a first direction.

Claims

1. A semiconductor device, comprising:

a first fin structure, a second fin structure and a third fin structure respectively protruding from a top surface of a substrate, wherein the first fin structure, the second fin structure and the third fin structure respectively extend along a first direction, the third fin structure and the first fin structure are aligned along the first direction, and the second fin structure and the third fin structure are arranged along a second direction, and wherein the first fin structure has a first end;

a patterned metal gate layer disposed on the substrate, wherein the patterned metal gate layer covers the first end of the first fin structure; and

a first epitaxial layer disposed at a side of the second fin structure, the second fin structure and the first epitaxial layer being arranged along the first direction, and the first epitaxial layer and the first fin structure being arranged along the second direction, wherein the first epitaxial layer has a second end, and the first end and the second end facing the first direction.

2. The semiconductor device according to claim 1, further comprises a fourth fin structure, and the first epitaxial layer is disposed between the first fin structure and the fourth fin structure.

3. The semiconductor device according to claim 2, wherein the fourth fin structure has a third end facing the first direction, and the patterned metal gate layer covers the third end.

4. The semiconductor device according to claim 1, wherein the patterned metal gate layer comprises a first metal gate and a second metal gate, and the first metal gate covers the first end of the first fin structure.

5. The semiconductor device according to claim 4, further comprising a second epitaxial layer disposed between the first fin structure and the third fin structure, wherein a length of the first epitaxial layer in the first direction is greater than a length of the second epitaxial layer in the first direction.

6. The semiconductor device according to claim 1, further comprising a fifth fin structure and a third epitaxial layer, the fifth fin structure protruding from the top surface of the substrate, the fifth fin structure and the second fin structure being aligned in a line, and the third epitaxial layer being disposed at a side of the fifth fin structure facing the second fin structure, wherein the third epitaxial layer has a fourth end facing the second end, and the patterned metal gate layer does not cover the fourth end.

7. The semiconductor device according to claim 6, wherein the third epitaxial layer is symmetrical to the first epitaxial layer with respect to the second direction.

8. The semiconductor device according to claim 6, wherein a space exists between the second end and the fourth end, and the space is greater than 70 nanometers.

9. The semiconductor device according to claim 6, wherein no fin structure exists between the second fin structure and the fifth fin structure.

10. A manufacturing method of a semiconductor device, comprising:

providing a first fin line and a second fin line respectively protruding from a top surface of a substrate, wherein the first fin line and the second fin line respectively extend along a first direction, and the first fin line and the second fin line are arranged along a second direction;

performing a fin line cutting process for cutting the first fin line and the second fin line, so as to form a first fin segment and a second fin segment, wherein the first fin segment has a first end, the second fin segment has a second end, and the first end and the second end face the first direction; and

forming a patterned conductive layer on the substrate, wherein the patterned conductive layer covers the first end of the first fin segment, and the patterned conductive layer does not cover the second end of the second fin segment.

11. The manufacturing method of the semiconductor device according to claim 10, wherein forming the patterned conductive layer comprises:

covering the first fin segment and the second fin segment with a conductive layer;

forming a hard mask layer on the conductive layer;

patterning the hard mask layer, so as to form a first hard mask pattern;

patterning the first hard mask pattern, so as to form a second hard mask pattern; and

transferring the second hard mask pattern to the conductive layer, so as to form the patterned conductive layer.

12. The manufacturing method of the semiconductor device according to claim 11, wherein forming the first hard mask pattern comprises forming an opening in the hard mask layer, and the opening exposes the conductive layer situated directly above the second end.

13. The manufacturing method of the semiconductor device according to claim 11, wherein forming the second hard mask pattern comprises forming an opening in the first hard mask pattern, and the opening exposes the conductive layer situated directly above the second end.

14. The manufacturing method of the semiconductor device according to claim 10, wherein the substrate further comprises a third fin line, the second fin line is disposed between the first fin line and the third fin line, and the fin line cutting process further comprises cutting the third fin line, so as to form a third fin segment.

15. The manufacturing method of the semiconductor device according to claim 10, wherein the patterned conductive layer comprises a first dummy gate and a second dummy gate, and the second dummy gate covers the first end of the first fin segment.

16. The manufacturing method of the semiconductor device according to claim 10, wherein cutting the second fin line further comprises forming a fourth fin segment, the fourth fin segment has a fourth end facing the second end, and the patterned conductive layer does not cover the fourth end.

17. The manufacturing method of the semiconductor device according to claim 16, wherein a space exists between the second end and the fourth end, and the space is greater than 70 nanometers.

18. The manufacturing method of the semiconductor device according to claim 16, wherein no fin segment exists between the second fin segment and the fourth fin segment.