Trench power MOSFET
First Claim
1. A device comprising:
- a semiconductor region of a first conductivity type;
a trench extending into the semiconductor region;
a field plate in the trench, wherein the field plate is conductive;
a first dielectric layer separating a bottom and sidewalls of the field plate from the semiconductor region;
a main gate in the trench, the main gate comprising;
a first portion overlapping the field plate and the first dielectric layer; and
a second portion, wherein an edge of the second portion contacts an edge of the first portion to form a distinguishable interface;
a second dielectric layer between and separating the main gate and the field plate from each other; and
a Doped Drain (DD) region of the first conductivity type, wherein the second portion of the main gate overlaps the DD region, wherein an entirety of the DD region is below a bottom surface of the main gate and higher than a bottom surface of the field plate, and wherein an inner edge of the second portion of the main gate is substantially vertically aligned to a vertical interface between the DD region and the first dielectric layer.
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Abstract
A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
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Citations
20 Claims
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1. A device comprising:
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a semiconductor region of a first conductivity type; a trench extending into the semiconductor region; a field plate in the trench, wherein the field plate is conductive; a first dielectric layer separating a bottom and sidewalls of the field plate from the semiconductor region; a main gate in the trench, the main gate comprising; a first portion overlapping the field plate and the first dielectric layer; and a second portion, wherein an edge of the second portion contacts an edge of the first portion to form a distinguishable interface; a second dielectric layer between and separating the main gate and the field plate from each other; and a Doped Drain (DD) region of the first conductivity type, wherein the second portion of the main gate overlaps the DD region, wherein an entirety of the DD region is below a bottom surface of the main gate and higher than a bottom surface of the field plate, and wherein an inner edge of the second portion of the main gate is substantially vertically aligned to a vertical interface between the DD region and the first dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A device comprising:
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a semiconductor region of a first conductivity type; a first dielectric layer extending into the semiconductor region; a field plate in the first dielectric layer, wherein the first dielectric layer comprises a bottom portion underlying the field plate, and a first sidewall portion and a second sidewall portion on opposite sidewalls of the field plate; a main gate comprising; a first portion overlapping the field plate and the first dielectric layer; and a second portion on a side of, and in contact with, the first portion, wherein the second portion extends horizontally beyond the field plate and both the first sidewall portion and the second sidewall portion of the first dielectric layer, and an edge of the second portion of the main gate contacts an edge of the first portion of the main gate to form a first substantially vertical distinguishable interface; a second dielectric layer between and separating the main gate and the field plate from each other; and a Doped Drain (DD) region of the first conductivity type contacting a sidewall of the first dielectric layer, wherein the second portion of the main gate overlaps the DD region, and a second substantially vertical interface between the first dielectric layer and the DD region is substantially vertically aligned to the first substantially vertical distinguishable interface. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A device comprising:
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a semiconductor region of a first conductivity type; a trench extending into the semiconductor region; a field plate in the trench, wherein the field plate is conductive; a first dielectric layer separating a bottom and sidewalls of the field plate from the semiconductor region; a main gate in the trench and overlapping the field plate, wherein the main gate extends laterally beyond edges of the first dielectric layer; a second dielectric layer between and separating the main gate and the field plate from each other; a Doped Drain (DD) region of the first conductivity type under the second dielectric layer; and a body region comprising; a first portion at a same level as a portion of the main gate, wherein the body region is of a second conductivity type opposite to the first conductivity type; and a second portion at a same level as, and contacting, the DD region, wherein the second portion of the body region forms a substantially vertical interface with the DD region, with the substantially vertical interface substantially aligned to an outer edge of the main gate. - View Dependent Claims (19, 20)
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Specification