Injection-locking PLL with frequency drift tracking and duty-cycle distortion cancellation

• US 10,110,239 B1
• Filed: 03/29/2018
• Issued: 10/23/2018
• Est. Priority Date: 10/12/2017
• Status: Active Grant

• Current Assignee: Oracle International Corporation (Oracle Corporation)
• Original Assignee: Oracle International Corporation (Oracle Corporation)
• Inventors: Shu, Guanghua, Liu, Frankie Y., Yang, Suwen, Shehadeh, Ziad Saleh, Chang, Eric Y.
• Primary Examiner(s): Malek, Leila
• Application Number:
  US15/940,681
• Time in Patent Office: 208 Days
• Field of Search: 375354, 375364, 331 57, 331177 R, 331 34
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03L 7/0998 using phase interpolation
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

During operation, the system uses a differential ring oscillator to generate the output clock signal. Next, the system uses a phase detector to detect errors comprising deviations between edges of the output clock signal and a reference clock signal. The system subsequently uses a frequency-tracking path to adjust a frequency of the differential ring oscillator based on the detected errors, wherein adjusting the frequency involves adjusting a supply voltage for the differential ring oscillator. The system also uses a phase-tracking path to adjust a phase of the differential ring oscillator based on the detected errors, wherein adjusting the phase involves selectively activating an injection pulse generator to inject pulses into the differential ring oscillator. Finally, the system uses a gating mechanism to periodically suppress the injected pulses produced by the injection pulse generator to enable the frequency-tracking path to detect and remediate frequency errors without interference from phase adjustments.

Claims

1. A clock generator implemented using an injection-locking phase-locked loop (PLL), comprising:

a reference input, which receives a reference clock signal;

a differential ring oscillator, which generates an output clock signal;

a phase detector, which detects errors comprising deviations between edges of the output clock signal and the reference clock signal;

a frequency-tracking path, which adjusts a frequency of the differential ring oscillator based on the detected errors, wherein the frequency is adjusted by adjusting a supply voltage for the differential ring oscillator;

a phase-tracking path, which adjusts a phase of the differential ring oscillator based on the detected errors, wherein the phase is adjusted by selectively activating an injection pulse generator;

the injection pulse generator, which injects pulses into the differential ring oscillator, wherein each injected pulse causes opposite polarity nodes in the differential ring oscillator to short when the opposite polarity nodes are proximate to a zero-crossing point; and

a gating mechanism, which periodically suppresses the injected pulses produced by the injection pulse generator to allow the frequency-tracking path to detect and remediate frequency errors without interference from concurrent phase adjustments.

2. The clock generator of claim 1, further comprising a frequency doubler, which doubles a frequency of the reference clock signal to produce a doubled reference clock signal, which is used to double an injection frequency.

3. The clock generator of claim 2, further comprising a duty-cycle correction circuit, which produces a duty-cycle correction signal D_CAL, which is used to correct the doubled reference clock signal.

4. The clock generator of claim 3, wherein the phase-tracking path comprises:

a digital phase accumulator, which accumulates detected errors from the phase detector to produce an output D_P;

an adder, which adds D_P to the duty-cycle correction signal D_CAL to produce a composite correction signal; and

a digitally controlled delay line (DCDL) that inserts a variable delay, which is determined based on the composite correction signal, into the doubled reference clock signal to produce a corrected doubled reference clock signal, which feeds into the injection pulse generator.

5. The clock generator of claim 1, wherein the frequency-tracking path comprises:

a digital accumulator (ACC_I), which accumulates detected errors from the phase detector;

a digital-to-analog converter (DAC), which converts an output of ACC_I into an analog voltage V_REF; and

a low-dropout (LDO) voltage regulator, which generates the supply voltage for the ring differential oscillator based on V_REF.

6. The clock generator of claim 1, wherein the gating mechanism is implemented using a multiplexer.

7. The clock generator of claim 1, wherein the phase detector is implemented using a bang-bang phase detector.

8. A method for generating an output clock signal using an injection-locking phase-locked loop (PLL), comprising:

receiving a reference clock signal;

using a differential ring oscillator to generate the output clock signal;

using a phase detector to detect errors comprising deviations between edges of the output clock signal and the reference clock signal;

using a frequency-tracking path to adjust a frequency of the differential ring oscillator based on the detected errors, wherein adjusting the frequency involves adjusting a supply voltage for the differential ring oscillator;

using a phase-tracking path to adjust a phase of the differential ring oscillator based on the detected errors, wherein adjusting the phase involves selectively activating an injection pulse generator to inject pulses into the differential ring oscillator, wherein each injected pulse causes opposite polarity nodes in the differential ring oscillator to short when the opposite polarity nodes are proximate to a zero-crossing point; and

using a gating mechanism to periodically suppress the injected pulses produced by the injection pulse generator to allow the frequency-tracking path to detect and remediate frequency errors without interference from concurrent phase adjustments.

9. The method of claim 8, further comprising using a frequency doubler to double a frequency of the reference clock signal to produce a doubled reference clock signal, which is used to double an injection frequency.

10. The method of claim 9, further comprising using a duty-cycle correction circuit to produce a duty-cycle correction signal D_CAL, which is used to correct the doubled reference clock signal.

11. The method of claim 10, wherein the phase-tracking path comprises:

a digital phase accumulator, which accumulates detected errors from the phase detector to produce an output D_P;

an adder, which adds D_P to the duty-cycle correction signal D_CAL to produce a composite correction signal; and

a digitally controlled delay line (DCDL) that inserts a variable delay, which is determined based on the composite correction signal, into the doubled reference clock signal to produce a corrected doubled reference clock signal, which feeds into the injection pulse generator.

12. The method of claim 8, wherein the frequency-tracking path comprises:

a digital accumulator (ACC_I), which accumulates detected errors from the phase detector;

a digital-to-analog converter (DAC), which converts an output of ACC_I into an analog voltage V_REF; and

a low-dropout (LDO) voltage regulator, which generates the supply voltage for the ring differential oscillator based on V_REF.

13. The method of claim 8, wherein the gating mechanism is implemented using a multiplexer.

14. The method of claim 8, wherein the phase detector is implemented using a bang-bang phase detector.

15. A computer system, comprising:

at least one processor and at least one associated memory; and

a clock generator that provides a clock signal for the at least one processor, wherein the clock generator is implemented using an injection-locking phase-locked loop (PLL), and includes;

a reference input, which receives a reference clock signal;

a differential ring oscillator, which generates an output clock signal;

a phase detector, which detects errors comprising deviations between edges of the output clock signal and the reference clock signal;

a frequency-tracking path, which adjusts a frequency of the differential ring oscillator based on the detected errors, wherein the frequency is adjusted by adjusting a supply voltage for the differential ring oscillator;

a phase-tracking path, which adjusts a phase of the differential ring oscillator based on the detected errors, wherein the phase is adjusted by selectively activating an injection pulse generator;

the injection pulse generator, which injects pulses into the differential ring oscillator, wherein each injected pulse causes opposite polarity nodes in the differential ring oscillator to short when the opposite polarity nodes are proximate to a zero-crossing point; and

a gating mechanism, which periodically suppresses the injected pulses produced by the injection pulse generator to allow the frequency-tracking path to detect and remediate frequency errors without interference from concurrent phase adjustments.

16. The computer system of claim 15, further comprising a frequency doubler, which doubles a frequency of the reference clock signal to produce a doubled reference clock signal, which is used to double an injection frequency.

17. The computer system of claim 16, further comprising a duty-cycle correction circuit, which produces a duty-cycle correction signal D_CAL, which is used to correct the doubled reference clock signal.

18. The computer system of claim 17, wherein the phase-tracking path comprises:

a digital phase accumulator, which accumulates detected errors from the phase detector to produce an output D_P;

an adder, which adds D_P to the duty-cycle correction signal D_CAL to produce a composite correction signal; and

a digitally controlled delay line (DCDL) that inserts a variable delay, which is determined based on the composite correction signal, into the doubled reference clock signal to produce a corrected doubled reference clock signal, which feeds into the injection pulse generator.

19. The computer system of claim 15, wherein the frequency-tracking path comprises:

a digital accumulator (ACC_I), which accumulates detected errors from the phase detector;

a digital-to-analog converter (DAC), which converts an output of ACC_I into an analog voltage V_REF; and

a low-dropout (LDO) voltage regulator, which generates the supply voltage for the ring differential oscillator based on V_REF.

20. The computer system of claim 15, wherein the gating mechanism is implemented using a multiplexer.