Method for accessing flash memory module and associated flash memory controller and memory device

• US 10,110,255 B2
• Filed: 04/25/2017
• Issued: 10/23/2018
• Est. Priority Date: 04/27/2016
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated Taiwan (Silicon Motion)
• Inventors: Yang, Tsung-Chieh, Hsu, Hong-Jung
• Primary Examiner(s): Ojha, Ajay
• Application Number:
  US15/495,997
• Publication Number:
  US 20170315868A1
• Time in Patent Office: 546 Days
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes

Abstract

A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.

Claims

1. A method for accessing a flash memory module, wherein the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip is a 3D flash memory chip, each flash memory chip includes a plurality of blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages, and the method comprises:

configuring the flash memory chips to set at least one first super block and at least one second super block of the flash memory chips;

allocating the at least one second super block to store temporary parity check codes generated by an encoding procedure during programming data into the at least one first super block;

reading a plurality of temporary parity check codes from the second super block;

generating a plurality of final parity check codes according to the temporary parity check codes, wherein each final parity check code is generated by using the temporary parity check codes corresponding to the data stored in nonadjacent word line groups of the first super block, and each word line group has a plurality of word lines; and

writing the plurality of final parity check codes into the first super block.

2. The method of claim 1, wherein the second super block is dedicated to store the temporary parity check codes generated by the encoding procedure during programming data into the at least one first super block.

3. The method of claim 1, wherein the first super block includes one multiple-level cell block of each flash memory chip among the flash memory chips, and the second super block includes one single-level cell (SLC) block of each flash memory chip among the flash memory chips.

4. The method of claim 3, wherein the multiple-level cell block is a triple-level cell (TLC) block or a quad-level cell (QLC) block.

5. The method of claim 1, further comprising:

during the data being written into the super block;

reading a portion of the data, which has been written into the first super block, from the first super block; and

reading at least one portion of the temporary parity check codes from the second super block, and using the at least one portion of the temporary parity check codes to perform error correction upon the portion of the data when an error occurs and cannot be corrected during reading the portion of the data.

6. The method of claim 1, further comprising:

after the final parity check code is written into the first super block, erasing contents of the second super block or marking the second super block as invalid/ineffective even if the data stored in the first super block is valid/effective.

7. The method of claim 1, further comprising:

after the final parity check code is written into the first super block;

reading a portion of the data from the first super block; and

when an error occurs and cannot be corrected during reading the portion of the data, reading the final parity check code from the first super block, and using the final parity check code to perform error correction upon the portion of the data.

8. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip is a 3D flash memory chip, each flash memory chip includes a plurality of blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages, and the flash memory controller comprises:

a memory, for storing a program code;

a microprocessor, for executing the program code to control access of the flash memory module; and

a codec;

wherein the microprocessor configures the flash memory chips to set at least one first super block and at least one second super block of the flash memory chips, and allocates the at least one second super block to store temporary parity check codes generated by an encoding procedure during programming data into the at least one first super block;

wherein the microprocessor reads a plurality of temporary parity check codes from the second super block, the codec generates a plurality of final parity check codes according to the temporary parity check codes, and the microprocessor writes the plurality of final parity check codes into the first super block, wherein each final parity check code is generated by using the temporary parity check codes corresponding to the data stored in nonadjacent word line groups of the first super block, and each word line group has a plurality of word lines.

9. The flash memory controller of claim 8, wherein the second super block is dedicated to store the temporary parity check codes generated by the encoding procedure during programming data into the at least one first super block.

10. The flash memory controller of claim 8, wherein the first super block includes one multiple-level cell block of each flash memory chip among the flash memory chips, and the second super block includes one single-level cell (SLC) block of each flash memory chip among the flash memory chips.

11. The flash memory controller of claim 10, wherein the multiple-level cell block is a triple-level cell (TLC) block or a quad-level cell (QLC) block.

12. The flash memory controller of claim 8, wherein during the data is written into the super block:

the microprocessor reads a portion of the data, which has been written into the first super block, from the first super block; and

the microprocessor reads at least one portion of the temporary parity check codes from the second super block, and the codec uses the at least one portion of the temporary parity check codes to perform error correction upon the portion of the data when an error occurs and cannot be corrected during reading the portion of the data.

13. The flash memory controller of claim 8, wherein after the final parity check code is written into the first super block, the microprocessor erases contents of the second super block or marks the second super block as invalid/ineffective even if the data stored in the first super block is valid/effective.

14. The flash memory controller of claim 8, wherein after the final parity check code is written into the first super block:

the microprocessor reads a portion of the data from the first super block; and

when an error occurs and cannot be corrected during reading the portion of the data, the microprocessor reads the final parity check code from the first super block, and the codec uses the final parity check code to perform error correction upon the portion of the data.

15. A memory device, comprising:

a flash memory module, wherein the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip is a 3D flash memory chip, each flash memory chip includes a plurality of blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages; and

a flash memory controller, for accessing the flash memory module;

wherein the flash memory controller configures the flash memory chips to set at least one first super block and at least one second super block of the flash memory chips, and allocates the at least one second super block to store temporary parity check codes generated by an encoding procedure during programming data into the at least one first super block;

wherein the flash memory controller reads a plurality of temporary parity check codes from the second super block, generates a plurality of final parity check codes according to the temporary parity check codes, and writes the plurality of final parity check codes into the first super block, wherein each final parity check code is generated by using the temporary parity check codes corresponding to the data stored in nonadjacent word line groups of the first super block, and each word line group has a plurality of word lines.

16. The memory device of claim 15, wherein the second super block is dedicated to store the temporary parity check codes generated by the encoding procedure during programming data into the at least one first super block.

17. The memory device of claim 15, wherein the first super block includes one multiple-level cell block of each flash memory chip among the flash memory chips, and the second super block includes one single-level cell (SLC) block of each flash memory chip among the flash memory chips.

18. The memory device of claim 17, wherein the multiple-level cell block is a triple-level cell (TLC) block or a quad-level cell (QLC) block.

19. The memory device of claim 15, wherein during the data is written into the super block:

the flash memory controller reads a portion of the data, which has been written into the first super block, from the first super block; and

the flash memory controller reads at least one portion of the temporary parity check codes from the second super block, and uses the at least one portion of the temporary parity check codes to perform error correction upon the portion of the data when an error occurs and cannot be corrected during reading the portion of the data.

20. The memory device of claim 15, wherein after the final parity check code is written into the first super block, the flash memory controller erases contents of the second super block or marks the second super block as invalid/ineffective even if the data stored in the first super block is valid/effective.

21. The memory device of claim 15, wherein after the final parity check code is written into the first super block:

the flash memory controller reads a portion of the data from the first super block; and

when an error occurs and cannot be corrected during reading the portion of the data, the flash memory controller reads the final parity check code from the first super block, and uses the final parity check code to perform error correction upon the portion of the data.