Packet-processing with CPPI DMA streaming interface ingress and egress ports

• US 10,110,573 B2
• Filed: 10/09/2017
• Issued: 10/23/2018
• Est. Priority Date: 07/08/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Mundra, Amritpal Singh, Beaudoin, Denis Roland
• Primary Examiner(s): Chang, Kenneth W
• Application Number:
  US15/728,035
• Publication Number:
  US 20180034790A1
• Time in Patent Office: 379 Days
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 63/0428 wherein the data content is protected, e.g. by encrypting or encapsulating the payload
• CPC Class Codes: H04L 63/0485 Networking architectures for enhanced packet encryption processing, e.g. offloading of IPsec packet processing or efficient security association look-up
• CPC Class Codes: H04L 63/08 for authentication of entities cryptographic mechanisms or cryptographic arrangements for entity authentication H04L9/32
• CPC Class Codes: H04L 9/0625 with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0637 Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM]
• CPC Class Codes: H04L 9/0643 Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
• CPC Class Codes: H04L 9/065 Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
• CPC Class Codes: H04L 9/0869 involving random numbers or seeds
• CPC Class Codes: H04L 9/3013 involving the discrete logarithm problem, e.g. ElGamal or Diffie-Hellman systems
• CPC Class Codes: H04L 9/32 including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
• CPC Class Codes: H04L 9/3236 using cryptographic hash functions
• CPC Class Codes: H04L 9/3239 involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD
• CPC Class Codes: H04L 9/3242 involving keyed hash functions, e.g. message authentication codes [MACs], CBC-MAC or HMAC
• CPC Class Codes: H04L 9/50 using hash chains, e.g. blockchains or hash trees
• CPC Class Codes: H04W 12/069 : using certificates or pre-shared keys

Abstract

An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.

Claims

1. A packet-processing electronic subsystem comprising:

(a) a first ingress port having a data input and a data output;

(b) a second ingress port having a data input and a data output;

(c) a first egress port having a data input and a data output;

(d) a second egress port having a data input and a data output, the first and second ingress ports and the first and second egress ports being separate from one another;

(e) scheduler circuitry having;

a first ingress input coupled to the first ingress port data output,

a second ingress input coupled to the second ingress port data output,

a first egress output coupled to the first egress port data input,

a second egress output coupled to second egress port data input,

a security context cache interface,

a packet header processor interface, and

an encryption interface;

(f) a security context cache coupled to the scheduler circuitry security context cache interface and having a control interface;

(g) a packet header processor coupled to the scheduler circuitry packet header processor interface and to the security context cache control interface;

(h) an encryption module coupled to the scheduler circuitry encryption interface and to the security context cache control interface; and

(i) in which the second ingress port is a Communication Processor Peripheral Interface (CPPI) direct memory access (DMA) streaming interface.

2. The subsystem of claim 1 in which the first ingress port is a packet accelerator (PA) Communication Processor Peripheral Interface (CPPI) streaming interface.

3. The subsystem of claim 1 in which the first egress port is a packet accelerator (PA) Communication Processor Peripheral Interface (CPPI) streaming interface.

4. A packet-processing electronic subsystem comprising:

(a) a first ingress port having a data input and a data output;

(b) a second ingress port having a data input and a data output;

(c) a first egress port having a data input and a data output;

(d) a second egress port having a data input and a data output, the first and second ingress ports and the first and second egress ports being separate from one another;

(e) scheduler circuitry having;

a first ingress input coupled to the first ingress port data output,

a second ingress input coupled to the second ingress port data output,

a first egress output coupled to the first egress port data input,

a second egress output coupled to second egress port data input,

a security context cache interface,

a packet header processor interface, and

an encryption interface;

(f) a security context cache coupled to the scheduler circuitry security context cache interface and having a control interface;

(g) a packet header processor coupled to the scheduler circuitry packet header processor interface and to the security context cache control interface; and

(h) an encryption module coupled to the scheduler circuitry encryption interface and to the security context cache control interface; and

(i) in which the second egress port is a Communication Processor Peripheral Interface (CPPI) direct memory access (DMA) streaming interface.

5. The subsystem of claim 4 in which the first ingress port is a packet accelerator (PA) Communication Processor Peripheral Interface (CPPI) streaming interface.

6. The subsystem of claim 4 in which the first egress port is a packet accelerator (PA) Communication Processor Peripheral Interface (CPPI) streaming interface.

7. A packet-processing electronic subsystem comprising:

(a) a first ingress port having a data input and a data output;

(b) a second ingress port having a data input and a data output;

(c) a first egress port having a data input and a data output;

(d) a second egress port having a data input and a data output, the first and second ingress ports and the first and second egress ports being separate from one another;

(e) scheduler circuitry having;

a first ingress input coupled to the first ingress port data output,

a second ingress input coupled to the second ingress port data output,

a first egress output coupled to the first egress port data input,

a second egress output coupled to second egress port data input,

a security context cache interface,

a packet header processor interface, and

an encryption interface;

(f) a security context cache coupled to the scheduler circuitry security context cache interface and having a control interface;

(g) a packet header processor coupled to the scheduler circuitry packet header processor interface and to the security context cache control interface; and

(h) an encryption module coupled to the scheduler circuitry encryption interface and to the security context cache control interface; and

(i) in which each of the data inputs and data outputs of the first and second ingress ports and the first and second egress ports are 32 bits wide.

8. The subsystem of claim 7 in which the first ingress port is a packet accelerator (PA) Communication Processor Peripheral Interface (CPPI) streaming interface.

9. The subsystem of claim 7 in which the first egress port is a packet accelerator (PA) Communication Processor Peripheral Interface (CPPI) streaming interface.