Integrated circuit testing

• US 10,114,073 B2
• Filed: 08/17/2015
• Issued: 10/30/2018
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ong, Adrian E.
• Primary Examiner(s): Tu, Christine T.
• Application Number:
  US14/827,983
• Publication Number:
  US 20160003904A1
• Time in Patent Office: 1,170 Days
• Field of Search: 714734, 714724, 714725, 714733, 455 41, 455558, 235492, 235487
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/31928 Formatter driver, receiver details G01R31/31924
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

Systems and methods of testing integrated circuits are disclosed. A system may include a data compression component to compress data received from an integrated circuit under test at a first clock frequency, to generate compressed data. The system may also include a data output component, operatively coupled to the data compression component, to convey the compressed data to automated testing equipment at a second clock frequency.

Claims

1. A system comprising:

a data compression component to compress data received from an integrated circuit under test at a first clock frequency, to generate compressed data; and

a data output component, operatively coupled to the data compression component, to convey the compressed data to automated testing equipment at a second clock frequency, wherein the first clock frequency provides testing of the integrated circuit at a higher frequency than the second clock frequency.

2. The system of claim 1, wherein the data compression component is to compare the received data to an expected data result and to communicate an output to the automated testing equipment.

3. The system of claim 2, wherein the data output component is included in a test module, the test module being one of a plurality of test modules included in a test array to test a plurality of integrated circuits.

4. The system of claim 3, wherein the test array comprises a memory to store the expected data result, and wherein the memory being shared by the plurality of test modules.

5. The system of claim 1, wherein the data compression component is to compress the data received from the integrated circuit responsive to whether an address of the data is even or odd.

6. The system of claim 1, wherein the data compression component is to compress the data received from the integrated circuit responsive to an invert odd or even bit mode.

7. The system of claim 1, wherein the data compression component is configured to compress the data received from the integrated circuit in a serial compression stage.

8. The system of claim 7, wherein the serial compression stage comprises multiple comparisons of the data received from the integrated circuit to an expected data value.

9. The system of claim 1, wherein the data compression component is to compress the data received from the integrated circuit in a parallel compression stage.

10. The system of claim 1, wherein the data compression component is to compress the data received from the integrated circuit in both a serial compression stage and a parallel compression stage.

11. The system of claim 1, wherein the data compression component is to compress the data received from the integrated circuit by a ratio of 4-to-1 or greater.

12. The system of claim 1, further comprising the automatic testing equipment, wherein the automatic testing equipment is coupled to the data output component to test the integrated circuit.

13. A system comprising:

a data compression component to compress data received from an integrated circuit to generate compressed data, the compression being responsive to an address within the integrated circuit from which the data was received, wherein the compression is performed at a first clock frequency; and

a data output component, operatively coupled with the data compression component, to convey the compressed data to the automated testing equipment, wherein the compressed data is conveyed at a second clock frequency different than the first clock frequency.

14. The system of claim 13, wherein the compression is further responsive to a mode in which odd bits or even bits are inverted.

15. The system of claim 13, further comprising two or more pins configured to receive an expected data result, and wherein the data compression component is to compare the received data to the expected data result and to communicate an output to the automated testing equipment.

16. The system of claim 13, wherein the compression is further responsive to expected data received from the automated testing equipment.

17. A method comprising:

compressing, by a test device, received data responsive to expected data, to generate compressed data, wherein the compression is performed at a first clock frequency; and

providing, by the test device, the compressed data to the automated testing equipment, wherein the compressed data is provided at a second clock frequency different than the first clock frequency.

18. The method of claim 17, wherein the received data is received from the integrated circuit at the first clock frequency and provided to the automated testing equipment at the second clock frequency, and wherein compressing the received data is responsive to an address within the integrated circuit from which the received data was received.