Method and apparatus for improving read performance of a solid state drive

• US 10,114,556 B2
• Filed: 10/02/2017
• Issued: 10/30/2018
• Est. Priority Date: 12/23/2014
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Ramalingam, Anand S.
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US15/723,072
• Publication Number:
  US 20180121092A1
• Time in Patent Office: 393 Days
• Field of Search: None
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A controller of a solid state drive initiates a repacking of data stored in a non-volatile memory of the solid state drive, wherein refreshing of the data stored in the non-volatile memory of the solid state drive is performed during the repacking of the data stored in the non-volatile memory of the solid state drive. Logical blocks are placed physically contiguously in an increasing order in pre-erased locations of the non-volatile memory of the solid state drive while the data stored in the non-volatile memory of the solid state drive is being repacked.

Claims

1. A method for improving performance of a solid state drive, the method comprising:

initiating, by a controller of the solid state drive, a repacking of data stored in a non-volatile memory of the solid state drive; and

performing the repacking of the data stored in the non-volatile memory of the solid state drive to refresh the solid state drive.

2. The method of claim 1, wherein the repacking is performed by placing logical blocks with consecutive numerically indicated addresses sequentially, starting from a lower numbered address and ending at a higher numbered address.

3. The method of claim 2, wherein the logical blocks are represented in a smaller page size in a host than the solid state drive.

4. The method of claim 3, wherein an indirection table in the solid state drive maintains pointers to physical memory addresses of most recent copies of valid data stored in the solid state drive, and wherein the indirection table represents a plurality of logical blocks in a same page size as the host.

5. The method of claim 1, wherein the solid state drive is comprised of a plurality of non-volatile memory chips, wherein there is only one channel for each non-volatile memory chip of the plurality of non-volatile memory chips, wherein there is only one chip select for each non-volatile memory chip of the plurality of non-volatile memory chips, and wherein parallel read requests cannot be handled by the one channel.

6. The method of claim 5, wherein each page size is 16 Kilobytes and requests from a host to the solid state drive are made in page sizes of 4 Kilobytes.

7. The method of claim 1, wherein the repacking of data in the solid state drive is performed periodically, and wherein logical blocks are placed physically contiguously in an increasing order in pre-erased locations of the non-volatile memory of the solid state drive during each periodic repacking of the data in the solid state drive.

8. An apparatus, comprising:

a plurality of non-volatile memory chips; and

a controller coupled to the plurality of non-volatile memory chips, wherein the controller is operable to;

initiate a repacking of data stored in the plurality of non-volatile memory chips; and

perform the repacking of the data stored in the plurality of non-volatile memory chips to refresh the non-volatile memory chips.

9. The apparatus of claim 8, wherein the repacking is performed by placing logical blocks with consecutive numerically indicated addresses sequentially, starting from a lower numbered address and ending at a higher numbered address.

10. The apparatus of claim 9, wherein the logical blocks are represented in a smaller page size in a host than the non-volatile memory chips.

11. The apparatus of claim 10, wherein an indirection table maintains pointers to physical memory addresses of most recent copies of valid data stored in the plurality of non-volatile memory chips, and wherein the indirection table represents a plurality of logical blocks in a same page size as the host.

12. The apparatus of claim 8, wherein there is only one channel for each non-volatile memory chip of the plurality of non-volatile memory chips, wherein there is only one chip select for each non-volatile memory chip of the plurality of non-volatile memory chips, and wherein parallel read requests cannot be handled by the one channel.

13. The apparatus of claim 12, wherein each page size is 16 Kilobytes and requests from a host to the apparatus are made in page sizes of 4 Kilobytes.

14. The apparatus of claim 8, wherein the repacking of data in the plurality of non-volatile memory chips is performed periodically, and wherein logical blocks are placed physically contiguously in an increasing order in pre-erased locations of the non-volatile memory chips during each periodic repacking of the data in the plurality of non-volatile memory chips.

15. A system, comprising:

a solid state drive comprising a plurality of non-volatile memory chips;

a display; and

a processor coupled to the solid state drive and the display, wherein, the solid state drive is operable to;

initiate a repacking of data stored in the plurality of non-volatile memory chips; and

perform the repacking of the data stored in the plurality of non-volatile memory chips to refresh the non-volatile memory chips.

16. The system of claim 15, wherein the repacking is performed by placing logical blocks with consecutive numerically indicated addresses sequentially, starting from a lower numbered address and ending at a higher numbered address.

17. The system of claim 16, wherein the logical blocks are represented in a smaller page size in a host than the solid state drive.

18. The system of claim 17, wherein an indirection table maintains pointers to physical memory addresses of most recent copies of valid data stored in the plurality of non-volatile memory chips, and wherein the indirection table represents a plurality of logical blocks in a same page size as a host operating system.

19. The system of claim 15, wherein there is only one channel for each non-volatile memory chip of the plurality of non-volatile memory chips, wherein there is only one chip select for each non-volatile memory chip of the plurality of non-volatile memory chips, and wherein parallel read requests cannot be handed by the one channel.

20. The system of claim 15, wherein the repacking of data in the plurality of non-volatile memory chips is performed periodically, and wherein logical blocks are placed physically contiguously in an increasing order in pre-erased locations of the plurality of non-volatile memory chips during each periodic repacking of the data in the plurality of non-volatile memory chips.