Command message generation and execution using a machine code-instruction
First Claim
1. A method, comprising:
- executing, by a processor of a particular machine, a single machine-code instruction of a processor instruction set of the processor, with the single machine-code instruction including an OP code and a plurality of arguments, with the OP code specifying to the processor the operation of the of the single machine-code instruction that includes generating a command message based on the plurality of arguments;
wherein the plurality of augments includes a reference into a command-message-building data structure stored in memory, a virtual address, and a copy position reference;
wherein said executing the single machine-code instruction by the processor includes generating the command message and initiating communication of the command message to the hardware accelerator, with said generating the command message including copying command information, that includes an identification of a plurality of operations, from the command-message-building data structure based on the reference into the command message at a position within the command message identified based on the copy position reference;
wherein a translation of the virtual address is included in the command message;
receiving, by the hardware accelerator, the command message that includes the command information that includes the identification of the plurality of operations; and
executing, by the hardware accelerator, the command message, with said executing the command message includes executing the plurality of operations.
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Abstract
In one embodiment, command message generation and execution using a machine code-instruction is performed. One embodiment includes a particular machine executing a single machine-code instruction including a reference into a command-message-building data structure stored in memory. This executing the single machine-code instruction includes generating a command message and initiating communication of the command message to a hardware accelerator, including copying command information from the command-message-building data structure based on the reference into the command message. The hardware accelerator receives and executes the command message. In one embodiment, the command message is message-switched from a processor to a hardware accelerator, such as, but not limited to, a memory controller, a table lookup unit, or a prefix lookup unit. In one embodiment, a plurality of threads share the command-message-building data structure. In one embodiment, a plurality of processors share the command-message-building data structure.
23 Citations
19 Claims
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1. A method, comprising:
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executing, by a processor of a particular machine, a single machine-code instruction of a processor instruction set of the processor, with the single machine-code instruction including an OP code and a plurality of arguments, with the OP code specifying to the processor the operation of the of the single machine-code instruction that includes generating a command message based on the plurality of arguments;
wherein the plurality of augments includes a reference into a command-message-building data structure stored in memory, a virtual address, and a copy position reference;
wherein said executing the single machine-code instruction by the processor includes generating the command message and initiating communication of the command message to the hardware accelerator, with said generating the command message including copying command information, that includes an identification of a plurality of operations, from the command-message-building data structure based on the reference into the command message at a position within the command message identified based on the copy position reference;
wherein a translation of the virtual address is included in the command message;receiving, by the hardware accelerator, the command message that includes the command information that includes the identification of the plurality of operations; and executing, by the hardware accelerator, the command message, with said executing the command message includes executing the plurality of operations. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An apparatus, comprising:
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a hardware accelerator; a memory-stored command message-building data structure; a processor that executes a single machine-code instruction of a processor instruction set of the processor, with the single machine-code instruction including an OP code and a plurality of arguments, with the OP code specifying to the processor the operation of the single machine-code instruction that includes generating a command message based on the plurality of arguments;
wherein the plurality of augments includes a reference into the memory-stored command message-building data structure, a virtual address, and a copy position reference;
wherein said executing the single machine-code instruction by the processor includes generating the command message and initiating communication of the command message to the hardware accelerator, with said generating the command message including copying command information, that includes an identification of a plurality of operations. from the memory-stored command-message-building data structure based on the reference into the command message at a position within the command message identified based on the copy position reference;
wherein a translation of the virtual address is included in the command message;wherein the hardware accelerator receives and executes the command message, with said executing the command message includes executing the plurality of operations. - View Dependent Claims (16, 17)
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18. An apparatus, comprising:
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a hardware accelerator that receives and executes command messages; a memory-stored command message-building data structure; a plurality of processors, with each particular processor of the plurality of processors executing a single machine-code instruction of a processor instruction set of the plurality of processors, with the single machine-code instruction including an OP code and a plurality of arguments, with the OP code specifying to said particular processor the operation of the single machine-code instruction that includes generating a command message based on the plurality of arguments;
wherein the plurality of augments includes a reference into the memory-stored command message-building data structure, a virtual address, and a copy position reference;
wherein said executing the single machine-code instruction includes generating the command message and initiating communication of the command message to the hardware accelerator, with said generating the command message including copying command information, that includes an identification of a plurality of operations, from the memory-stored command-message-building data structure based on the reference into the command message at a position within the command message identified based on the copy position reference;
wherein each of the plurality of processors has shared-access to the memory-stored command message-building data structure;
wherein a translation of the virtual address is included in the command message. - View Dependent Claims (19)
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Specification