Concurrent testing of PCI express devices on a server platform
First Claim
1. A computer-implemented method for testing peripheral component interconnect express (PCIe) devices, the method comprising:
- detecting that a plurality of PCIe devices have been inserted into one or more PCIe buses of a data processing system;
in response to the detection, scanning all PCIe buses of the data processing system to discover the plurality of PCIe devices;
for each of the PCIe devices discovered,repairing and retraining a PCIe link associated with the PCIe device, without rebooting the data processing system, andloading a device driver instance for the PCIe device to be hosted by an operating system;
executing a test routine to concurrently test the plurality of PCIe devices via respective device driver instances;
in response to a signal indicating that the execution of the test routine has been completed, unloading the device driver instances of the PCIe devices; and
communicating with the operating system to remove the Me devices from a namespace of the operating system, without rebooting the data processing system.
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Accused Products
Abstract
A method for testing peripheral component interconnect express (PCIe) devices is provided. The method implemented at a PCIe testing system detects that one or more PCIe devices have been inserted into one or more PCIe buses of a data processing system. In response to the detection, the PCIe testing system scans all PCIe buses of the data processing system to discover the one or more PCIe devices. For each of the PCIe devices discovered, the PCIe testing system repairs and retrains a PCIe link associated with the PCIe device, without rebooting the data processing system. The PCIe testing system loads a device driver instance for the PCIe device to be hosted by an operating system. The PCIe testing system then executes a test routine to concurrently test the one or more PCIe devices via the respective device driver instances.
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Citations
24 Claims
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1. A computer-implemented method for testing peripheral component interconnect express (PCIe) devices, the method comprising:
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detecting that a plurality of PCIe devices have been inserted into one or more PCIe buses of a data processing system; in response to the detection, scanning all PCIe buses of the data processing system to discover the plurality of PCIe devices; for each of the PCIe devices discovered, repairing and retraining a PCIe link associated with the PCIe device, without rebooting the data processing system, and loading a device driver instance for the PCIe device to be hosted by an operating system; executing a test routine to concurrently test the plurality of PCIe devices via respective device driver instances; in response to a signal indicating that the execution of the test routine has been completed, unloading the device driver instances of the PCIe devices; and communicating with the operating system to remove the Me devices from a namespace of the operating system, without rebooting the data processing system. - View Dependent Claims (2, 3, 4)
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5. A computer-implemented method for testing peripheral component interconnect express (PCIe) devices, the method comprising:
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detecting that a plurality of PCIe devices have been inserted into one or more PCIe buses of a data processing system; in response to the detection, scanning all Pete buses of the data processing system to discover the plurality of PCIe devices; for each of the PCIe devices discovered, repairing and retraining a PCIe link associated with the PCIe device, without rebooting the data processing system, wherein repairing and retraining a PCIe link associated with the PCIe device comprises; setting a first clock configuration bit in a first PCIe link control register of the PCIe device, and setting a second clock configuration bit in a second PCIe link control register of a root complex device coupled to the PCIe device to recover a PCIe reference clock configuration, and loading a device driver instance for the PCIe device to be hosted by an operating system; and executing a test routine to concurrently test the plurality of PCIe devices via respective device driver instances. - View Dependent Claims (6, 7, 8)
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9. A non-transitory machine-readable medium having instructions stored therein, which when executed by a processor, cause the processor to perform operations for testing PCIe devices, the operations comprising:
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detecting that a plurality of PCIe devices have been inserted into one or more PCIe buses of a data processing system; in response to the detection, scanning all PCIe buses of the data processing system to discover the plurality of PCIe devices; for each of the PCIe devices discovered, repairing and retraining a PCIe link associated with the PCIe device, without rebooting the data processing system, and loading a device driver instance for the PCIe device to be hosted by an operating system; executing a test routine to concurrently test the plurality of PCIe devices via respective device driver instances; in response to a signal indicating that the execution of the test routine has been completed, unloading the device driver instances of the PCIe devices; and communicating with the operating system to remove the PCIe devices from a namespace of the operating system, without rebooting the data processing system. - View Dependent Claims (10, 11, 12)
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13. A non-transitory machine-readable medium having instructions stored therein, which when executed b a processor, cause the processor to perform operations for testing PCIe devices, the operations comprising:
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detecting that a plurality of PCIe devices have been inserted into one or more PCIe buses of a data processing system; in response to the detection, scanning all PCIe buses of the data processing s stem to discover the plurality of PCIe devices; for each of the PCIe devices discovered, repairing and retraining a PCIe link associated with the PCIe device, without rebooting the data processing system, wherein repairing and retraining a PCIe link associated with the PCIe device comprises; setting a first clock configuration bit in a first PCIe link control register of the PCIe device, and setting a second clock configuration bit in a second PCIe link control register of a root complex device coupled to the PCIe device to recover a PCIe reference clock configuration, and loading a device driver instance for the PCIe device to be hosted by an operating system; and executing a test routine to concurrently test the plurality of PCIe devices via respective device driver instances. - View Dependent Claims (14, 15, 16)
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17. A system, comprising:
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a processor; and a memory coupled to the processor for storing instructions, which when executed from the memory, cause the processor to perform operations for testing PCIe devices, the operations including; detecting that a plurality of PCIe devices have been inserted into one or more PCIe buses of a data processing system; in response to the detection, scanning all PCIe buses of the data processing system to discover the plurality of PCIe devices; for each of the PCIe devices discovered, repairing and retraining a PCIe link associated with the PCIe device, without rebooting the data processing system, and loading a device driver instance for the PCIe device to be hosted by an operating system; executing a test routine to concurrently test the plurality of PCIe devices via respective device driver instances, in response to a signal indicating that the execution of the test routine has been completed, unloading the device driver instances of the PCIe devices; and communicating with the operating system to remove the PCIe devices from a namespace of the operating system, without rebooting the data processing system. - View Dependent Claims (18, 19, 20)
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21. A system, comprising:
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a processor; and a memory coupled to the processor for storing instructions, which when executed from the memory, cause the processor to perform operations for testing PCIe devices, the operations including; detecting that a plurality of PCIe devices have been inserted into one or more PCIe buses of a data processing system; in response to the detection, scanning all PCIe buses of the data processing system to discover the plurality of PCIe devices; for each of the PCIe devices discovered, repairing and retraining a PCIe link associated with the PCIe device, without rebooting the data processing system, wherein repairing and retraining a PCIe link associated with the PCIe device comprises; setting a first clock configuration bit in a first PCIe link control register of the PCIe device, and setting a second clock configuration bit in a second PCIe link control register of a root complex device coupled to the PCIe device to recover a PCIe reference clock configuration, and loading a device driver instance for the PCIe device to be hosted by an operating system; and executing a test routine to concurrently test the plurality of PCIe devices via respective device driver instances. - View Dependent Claims (22, 23, 24)
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Specification