Efficient buffer allocation for NAND write-path system

• US 10,114,742 B1
• Filed: 08/28/2015
• Issued: 10/30/2018
• Est. Priority Date: 09/05/2014
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Yuan, Wei-Hao, Ho, Chun Hok, Yen, Johnson
• Primary Examiner(s): Thammavong, Prasith
• Assistant Examiner(s): Blust, Jason W
• Application Number:
  US14/839,831
• Time in Patent Office: 1,159 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A first write data and a second write data destined for a first solid state storage channel and a second solid state storage channel, respectively, is received. The first write data is chopped using a chopping factor in order to obtain (1) a first piece of chopped write data destined for the first solid state storage channel and (2) a second piece of chopped write data destined for the first solid state storage channel. The second write data is chopped using the chopping factor in order to obtain (1) a third piece of chopped write data destined for the second solid state storage channel and (2) a fourth piece of chopped write data destined for the second solid state storage channel.

Claims

1. A system, comprising:

a non-volatile memory comprising a group of solid state storage cells;

a memory controller coupled with the non-volatile memory, wherein the memory controller is configured to;

receive a first write data destined for a first solid state storage channel and a second write data destined for a second solid state storage channel, wherein the first solid state storage channel is different than the second solid state storage channel;

chop the first write data using at least a chopping factor in order to obtain (1) a first piece of chopped write data destined for the first solid state storage channel and (2) a second piece of chopped write data destined for the first solid state storage channel, wherein the first piece of chopping write data is addressed prior to the second piece of chopped write data;

chop the second write data using at least the chopping factor in order to obtain (1) a third piece of chopped write data destined for the second solid state storage channel and (2) a fourth piece of chopped write data destined for the second solid state storage channel, wherein the third piece of chopped write data is addressed prior to the fourth piece of chopped write data;

transfer the first piece of chopped write data to a write-path system (“

WRP”

);

store, in a first channel buffer in the WRP, the first piece of chopped write data, wherein the first channel buffer is a same size as the first piece of chopped write data;

after transferring the first piece of chopped write data, transfer the third piece of chopped write data to the WRP;

store, in a second channel buffer in the WRP, the third piece of chopped write data, wherein the second channel buffer is a same size as the third piece of chopped write data;

after transferring the third piece of chopped write data, transfer the second piece of chopped write data to the WRP;

store, in the first channel buffer in the WRP, the second piece of chopped write data;

after transferring the second piece of chopped write data, transfer the fourth piece of chopped write data to the WRP; and

store, in the second channel buffer in the WRP, the fourth piece of chopped write data.

2. The system as recited in claim 1, wherein the first solid state storage channel is a NAND channel in the non-volatile memory.

3. The system as recited in claim 2, wherein the first write data is equal to a NAND page size for NAND channels.

4. The system as recited in claim 3, wherein the WRP is coupled to n NAND channels.

5. The system as recited in claim 4, wherein the chopping factor is based at least in part on n.

6. The system as recited in claim 5, wherein the chopping factor is less than n.

7. The system as recited in claim 2, wherein the first write data is received at a throughput X from a buffer manager system (“

BM”

).

8. The system as recited in claim 7, wherein the first piece of chopped write data is written at a throughput Y to a NAND channel.

9. The system as recited in claim 8, wherein the chopping factor is based at least in part on X and based at least in part on Y.

10. The system as recited in claim 9, wherein the chopping factor is based at least in part on dividing the throughput X associated with a BM by the throughput Y associated with a NAND channel.

11. The system as recited in claim 3, wherein a reduced size of the first piece of chopped write data is based at least in part on the NAND page size for NAND channels divided by the chopping factor.

12. The system as recited in claim 11, wherein each channel buffer is of the reduced size.

13. The system as recited in claim 12, further comprising a designed WRP based on channel buffers of the reduced size has lower area than a WRP based on channel buffers of the NAND page size.

14. The system as recited in claim 13, further comprising a designed WRP based on channel buffers of the reduced size has lower static power consumption than a WRP based on channel buffers of the NAND page size.

15. A method, comprising:

receiving a first write data destined for a first solid state storage channel and a second write data destined for a second solid state storage channel, wherein the first solid state storage channel is different than the second solid state storage channel;

chopping the first write data using at least a chopping factor in order to obtain (1) a first piece of chopped write data destined for the first solid state storage channel and (2) a second piece of chopped write data destined for the first solid state storage channel, wherein the first piece of chopping write data is addressed prior to the second piece of chopped write data;

chopping the second write data using at least the chopping factor in order to obtain (1) a third piece of chopped write data destined for the second solid state storage channel and (2) a fourth piece of chopped write data destined for the second solid state storage channel, wherein the third piece of chopped write data is addressed prior to the fourth piece of chopped write data;

transferring the first piece of chopped write data to a write-path system (“

WRP”

);

storing, in a first channel buffer in the WRP, the first piece of chopped write data, wherein the first channel buffer is a same size as the first piece of chopped write data;

after transferring the first piece of chopped write data, transferring the third piece of chopped write data to the WRP;

storing, in a second channel buffer in the WRP, the third piece of chopped write data, wherein the second channel buffer is a same size as the third piece of chopped write data;

after transferring the third piece of chopped write data, transferring the second piece of chopped write data to the WRP;

storing, in the first channel buffer in the WRP, the second piece of chopped write data;

after transferring the second piece of chopped write data, transferring the fourth piece of chopped write data to the WRP; and

storing, in the second channel buffer in the WRP, the fourth piece of chopped write data.

16. The method as recited in claim 15, wherein the first solid state storage channel is a NAND channel in a non-volatile memory.

17. The method as recited in claim 16, wherein the chopping factor is based at least in part on dividing X throughput associated with a BM by Y throughput associated with a NAND channel.

18. The method as recited in claim 17, wherein a reduced size of the first piece of chopped write data is based at least in part on a NAND page size for NAND channels divided by the chopping factor.