Cache memory system and method for accessing cache line

• US 10,114,749 B2
• Filed: 05/26/2017
• Issued: 10/30/2018
• Est. Priority Date: 11/27/2014
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Tu, Zhenxi, Xia, Jing
• Primary Examiner(s): Rutz, Jared I
• Assistant Examiner(s): Doan, Khoa D
• Application Number:
  US15/606,428
• Publication Number:
  US 20170262372A1
• Time in Patent Office: 522 Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0846 Cache with multiple tag or data arrays being simultaneously accessible
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache

Abstract

A cache memory system is provided. The cache memory system includes multiple upper level caches and a current level cache. Each upper level cache includes multiple cache lines. The current level cache includes an exclusive tag random access memory (Exclusive Tag RAM) and an inclusive tag random access memory (Inclusive Tag RAM). The Exclusive Tag RAM is configured to preferentially store an index address of a cache line that is in each upper level cache and whose status is unique dirty (UD). The Inclusive Tag RAM is configured to store an index address of a cache line that is in each upper level cache and whose status is unique clean (UC), shared clean (SC), or shared dirty (SD).

Claims

1. A cache memory system, comprising:

multiple upper level caches, wherein each upper level cache comprises multiple cache lines; and

a current level cache comprising an exclusive tag random access memory (Exclusive Tag RAM) and an inclusive tag random access memory (Inclusive Tag RAM), wherein the Exclusive Tag RAM is configured to preferentially store an index address of a first cache line that is in each upper level cache and whose status is unique dirty (UD), wherein the Inclusive Tag RAM is configured to store an index address of a second cache line that is in each upper level cache and whose status is unique clean (UC), shared clean (SC), or shared dirty (SD), and wherein data of the second cache line is backed up and stored in the current level cache.

2. The cache memory system according to claim 1, wherein the multiple upper level caches comprise a first cache and a second cache,

wherein the current level cache comprises a data random access memory (Data RAM),

wherein the data of the second cache line is backed up and stored in the Data RAM,

wherein the first cache is configured to send a request for accessing a third cache line to the current level cache, and

wherein the current level cache is configured to:

determine that an index address of the third cache line is in the Exclusive Tag RAM or the Inclusive Tag RAM after receiving the request for accessing the third cache line sent by the first cache;

determine a status of the third cache line; and

determine to send, to the first cache according to the status of the third cache line, data that is of the third cache line and that is obtained from the second cache or data that is of the third cache line and that is backed up and stored in the Data RAM of the current level cache.

3. The cache memory system according to claim 2, wherein the current level cache is further configured to:

send the data that is of the third cache line and that is obtained from the second cache to the first cache when determining that the status of the third cache line is UD;

send the data that is of the third cache line and that is backed up and stored in the Data RAM of the current level cache to the first cache when determining that the status of the third cache line is SC or SD;

send a request for accessing the data of the third cache line to the second cache when determining that the status of the third cache line is UC;

send the data that is of the third cache line and that is obtained from the second cache to the first cache when the data of the third cache line sent by the second cache is received;

or

send the data that is of the third cache line and that is backed up and stored in the Data RAM of the current level cache to the first cache when an indication, sent by the second cache, for skipping sending the data of the third cache line is received.

4. The cache memory system according to claim 2, wherein the current level cache further comprises a status random access memory (Status RAM), wherein the Status RAM is configured to record a status of a cache line whose index address is in the Exclusive Tag RAM or the Inclusive Tag RAM, and wherein the current level cache is configured to determine the status of the third cache line according to the Status RAM.

5. The cache memory system according to claim 1, wherein when a size of space, in the Exclusive Tag RAM, occupied by the index address of the first cache line reaches a maximum capacity value of the Exclusive Tag RAM, the Inclusive Tag RAM is further configured to store an index address of a fourth cache line that is in each upper level cache and whose status is UD, wherein the index address of the fourth cache line cannot be stored in the Exclusive Tag RAM, and wherein data of the fourth cache line is backed up and stored in the current level cache.

6. The cache memory system according to claim 1, wherein the UC state is used to indicate that a cache line in the UC state exists only in one cache of the cache memory system, and the cache line in the UC state comprises clean data,

wherein the UD state is used to indicate that a cache line in the UD state exists only in one cache of the cache memory system, and the cache line in the UD state comprises dirty data,

wherein the SC state is used to indicate that a cache line in the SC state exists in multiple caches of the cache memory system, and the cache line in the SC state comprises clean data, and

wherein the SD state is used to indicate that a cache line in the SD state exists in multiple caches of the cache memory system, and the cache line in the SD state comprises dirty data.

7. The cache memory system according to claim 1, wherein the upper level cache is a level N cache, wherein the current level cache is a level N+1 cache, and wherein N is a natural number.

8. A method for accessing a cache line in a cache memory system, wherein the cache memory system comprises multiple upper level caches and a current level cache, wherein each upper level cache comprises multiple cache lines, wherein the multiple upper level caches comprise a first cache and a second cache, wherein the current level cache comprises an exclusive tag random access memory (Exclusive Tag RAM) and an inclusive tag random access memory (Inclusive Tag RAM), wherein the Exclusive Tag RAM is configured to preferentially store an index address of a first cache line that is in each upper level cache and whose status is unique dirty (UD), wherein the Inclusive Tag RAM is configured to store an index address of a second cache line that is in each upper level cache and whose status is unique clean (UC), shared clean (SC), or shared dirty (SD), wherein data of the second cache line is backed up and stored in the current level cache, and wherein the method comprises:

sending, by the first cache, a request for accessing a third cache line to the current level cache;

determining, by the current level cache, that an index address of the third cache line is in the Exclusive Tag RAM or the Inclusive Tag RAM after receiving the request for accessing the third cache line;

determining, by the current level cache, a status of the third cache line; and

determining, by the current level cache according to the status of the third cache line, to send, to the first cache, data that is of the third cache line and that is obtained from the second cache or data that is of the third cache line and that is backed up and stored in the current level cache.

9. The method according to claim 8, wherein determining, by the current level cache according to the status of the third cache line, to send, to the first cache, data that is of the third cache line and that is obtained from the second cache or data that is of the third cache line and that is backed up and stored in the current level cache comprises:

sending, by the current level cache, the data that is of the third cache line and that is obtained from the second cache to the first cache when determining that the status of the third cache line is UD;

sending, by the current level cache, the data that is of the third cache line and that is backed up and stored in the current level cache to the first cache when determining that the status of the third cache line is SC or SD;

sending, by the current level cache, a request for accessing the data of the third cache line to the second cache when determining that the status of the third cache line is UC;

sending, by the current level cache, the data that is of the third cache line and that is obtained from the second cache to the first cache when the data of the third cache line sent by the second cache is received;

or

sending, by the current level cache, the data that is of the third cache line and that is backed up and stored in the current level cache to the first cache when an indication, sent by the second cache, for skipping sending the data of the third cache line is received.

10. The method according to claim 9, wherein sending, by the current level cache, the data that is of the third cache line and that is obtained from the second cache to the first cache when determining that the status of the third cache line is UD comprises:

sending, by the current level cache, a request for accessing the data of the third cache line to the second cache;

sending, by the second cache, the data of the third cache line stored in the second cache to the current level cache after receiving the request for accessing the data of the third cache line; and

sending, by the current level cache, the received data of the third cache line to the first cache.

11. The method according to claim 8, wherein determining, by the current level cache, the status of the third cache line comprises determining, by the current level cache, the status of the third cache line according to a status random access memory (Status RAM) of the current level cache, and wherein the Status RAM is configured to record a status of a cache line whose index address is in the Exclusive Tag RAM or the Inclusive Tag RAM.

12. The method according to claim 8, further comprising:

establishing, in the Inclusive Tag RAM, an index address that is of the first cache line and that is in the current level cache when the status of the first cache line whose index address is in the Exclusive Tag RAM changes from UD to SC, SD, or UC, backing up and storing data that is of the first cache line and that resides in one cache of the multiple upper level caches into the current level cache, and deleting the index address that is of the first cache line and that is in the Exclusive Tag RAM; and

establishing, in the Exclusive Tag RAM, an index address of the second cache line in the upper level cache when the status of the second cache line whose index address is in the Inclusive Tag RAM changes from SC, SD, or UC to UD, and deleting the data that is of the second cache line and that is backed up and stored in the current level cache and the index address that is of the second cache line and that is in the Inclusive Tag RAM.

13. The method according to claim 8, wherein the UC state is used to indicate that a cache line in the UC state exists only in one cache of the cache memory system, and the cache line in the UC state comprises clean data,

wherein the UD state is used to indicate that a cache line in the UD state exists only in one cache of the cache memory system, and the cache line in the UD state comprises dirty data,

wherein the SC state is used to indicate that a cache line in the SC state exists in multiple caches of the cache memory system, and the cache line in the SC state comprises clean data, and

wherein the SD state is used to indicate that a cache line in the SD state exists in multiple caches of the cache memory system, and the cache line in the SD state comprises dirty data.

14. The method according to claim 8, wherein the upper level cache is a level N cache, wherein the current level cache is a level N+1 cache, and wherein N is a natural number.