Method and system for implementing cache size estimations
First Claim
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1. A method implemented with a processor for performing cache estimation, comprising:
- generating a list of cache sizes, the list of cache sizes corresponding to different sizes of caches, the caches comprising one or more storage components;
initializing a hyperloglog (HLL) for each cache size on the list of cache sizes, wherein a first HLL is initialized for a first cache having a first cache size and a second HLL is initialized for a second cache having a second cache size, wherein the first cache size is different than the second cache size;
performing cache estimation using the HLL by representing a change of state of the HLL as a cache miss and a non-change of state of the HLL as a cache hit;
computing, using the HLL, a miss rate curve (MRC) from a count of the cache miss and the cache hit; and
changing a size of a cache based at least in part on a MRC value determined from the MRC computed by the HLL.
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Abstract
Disclosed is an improved approach to implement memory-efficient cache size estimations. A HyperLogLog is used to efficiently approximate an MRC with sufficient granularity to size caches.
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Citations
30 Claims
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1. A method implemented with a processor for performing cache estimation, comprising:
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generating a list of cache sizes, the list of cache sizes corresponding to different sizes of caches, the caches comprising one or more storage components; initializing a hyperloglog (HLL) for each cache size on the list of cache sizes, wherein a first HLL is initialized for a first cache having a first cache size and a second HLL is initialized for a second cache having a second cache size, wherein the first cache size is different than the second cache size; performing cache estimation using the HLL by representing a change of state of the HLL as a cache miss and a non-change of state of the HLL as a cache hit; computing, using the HLL, a miss rate curve (MRC) from a count of the cache miss and the cache hit; and changing a size of a cache based at least in part on a MRC value determined from the MRC computed by the HLL. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computer program product embodied on a computer readable medium, the computer readable medium having stored thereon a sequence of instructions which, when executed by a processor causes the processor to execute a method for implementing cache estimation, the method comprising:
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generating a list of cache sizes, the list of cache sizes corresponding to different sizes of caches, the caches comprising one or more storage components; initializing a hyperloglog (HLL) for each cache size on the list of cache sizes, wherein a first HLL is initialized for a first cache having a first cache size and a second HLL is initialized for a second cache having a second cache size, wherein the first cache size is different than the second cache size; performing cache estimation using the HLL by representing a change of state of the HLL as a cache miss and a non-change of state of the HLL as a cache; computing, using the HLL, a miss rate curve (MRC) from a count of the cache miss and the cache hit; and changing a size of a cache based at least in part on a MRC value determined from the MRC computed by the HLL. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A system for performing cache estimation, comprising:
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a computer processor to execute a set of program code instructions; and a memory to hold the program code instructions, in which the program code instructions comprises program code to perform;
generating a list of cache sizes, the list of cache sizes corresponding to different sizes of caches, the caches comprising one or more storage components;
initializing a hyperloglog (HLL) for each cache size on the list of cache sizes, wherein a first HLL is initialized for a first cache having a first cache size and a second HLL is initialized for a second cache having a second cache size, wherein the first cache size is different than the second cache size;
performing cache estimation using the HLL by representing a change of state of the HLL as a cache miss and a non-change of state of the HLL as a cache hit;
computing, using the HLL, a miss rate curve (MRC) from a count of the cache miss and the cache hit; and
changing a size of a cache based at least in part on a MRC value determined from the MRC computed by the HLL. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification