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Display controller system

  • US 10,115,354 B2
  • Filed: 05/26/2016
  • Issued: 10/30/2018
  • Est. Priority Date: 09/15/2009
  • Status: Active Grant
First Claim
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1. A display device assembly comprising:

  • a CPU memory;

    an image memory;

    a backplane comprising a plurality of pixel electrodes arranged in a series of lines; and

    a display controller comprisingtwo buffers,a look-up table, anda memory controller configured to transfer image data from the CPU memory to the two buffers and the image memory;

    wherein the display controller is configured to compare first image data and second image data of the image memory, to select driving waveforms for each pixel electrode in a given line for converting a first image to a second image, and to forward voltage data of the driving waveforms to the backplane to be applied to each of the pixels in the given line, andwherein the memory controller is configured to transfer a first set of image data to the image memory when one of the two buffers is full and to simultaneously transfer a second set of image data from the CPU memory to the other of the two buffers after the voltage data is forwarded by the display controller.

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