Memory device comprising electrically floating body transistor
First Claim
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1. A method of operating an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising:
- a plurality of said semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising;
a floating body region configured to be charged to a level indicative of a state of the memory cell;
a first region in electrical contact with said floating body region, located at a surface of said floating body region;
a second region in electrical contact with said floating body region, located at a surface of said floating body region, spaced apart from said first region;
a gate positioned between said first region and said second region; and
a third region in electrical contact with said floating body region, located below said floating body region;
said method comprising;
selecting said third region of at least one of said semiconductor memory cells in at least one of said at least two memory sub-arrays; and
operating said at least one of said memory sub-arrays independently of operation of a remainder of said at least two memory sub-arrays not selected.
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Abstract
A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.
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Citations
11 Claims
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1. A method of operating an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising:
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a plurality of said semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising; a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region, located at a surface of said floating body region; a second region in electrical contact with said floating body region, located at a surface of said floating body region, spaced apart from said first region; a gate positioned between said first region and said second region; and a third region in electrical contact with said floating body region, located below said floating body region; said method comprising; selecting said third region of at least one of said semiconductor memory cells in at least one of said at least two memory sub-arrays; and operating said at least one of said memory sub-arrays independently of operation of a remainder of said at least two memory sub-arrays not selected. - View Dependent Claims (2, 3, 4, 5)
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6. A method of operating an array of semiconductor memory cells, the array comprising a plurality of said semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising:
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a floating body region configured to be charged to a level indicative of a state of the memory cell; and a buried well region contacting said floating body region; said method comprising; selecting at least one of said at least one column or at least one row; and selecting at least one of said buried well regions; and disabling at least one of said plurality of said semiconductor cells not located in the at least one column or at least one row having been selected; wherein said disabling comprises removing a bias from said buried well region contacting said floating body region of said at least one of said plurality of said semiconductor cells not located in the at least one column or at least one row having been selected. - View Dependent Claims (7, 8, 9, 10, 11)
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Specification