Memory device comprising electrically floating body transistor

• US 10,115,451 B2
• Filed: 09/21/2017
• Issued: 10/30/2018
• Est. Priority Date: 08/15/2014
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Han, Jin-Woo, Berger, Neal, Widjaja, Yuniarto
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US15/712,041
• Publication Number:
  US 20180012646A1
• Time in Patent Office: 404 Days
• Field of Search: 365 51
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

Claims

1. A method of operating an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising:

a plurality of said semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising;

a floating body region configured to be charged to a level indicative of a state of the memory cell;

a first region in electrical contact with said floating body region, located at a surface of said floating body region;

a second region in electrical contact with said floating body region, located at a surface of said floating body region, spaced apart from said first region;

a gate positioned between said first region and said second region; and

a third region in electrical contact with said floating body region, located below said floating body region;

said method comprising;

selecting said third region of at least one of said semiconductor memory cells in at least one of said at least two memory sub-arrays; and

operating said at least one of said memory sub-arrays independently of operation of a remainder of said at least two memory sub-arrays not selected.

2. The method of operating an array of semiconductor memory cells of claim 1, wherein said selecting at least one of said at least two memory sub-arrays is performed by applying a first bias condition to said at least one of said memory sub-arrays and a second bias condition to at least one of said at least two memory sub-arrays not selected, wherein said first bias condition is different from said second bias condition.

3. The method of operating an array of semiconductor memory cells of claim 1, further comprising applying a bias to said third region within one of said at least two memory sub-arrays to maintain states of said semiconductor memory cells in said one of said at least two memory sub-arrays.

4. The method of operating an array of semiconductor memory cells of claim 1, further comprising applying a first ramp rate for reading said state of a memory cell in said array and applying a second ramp rate for writing said state to said memory cell, wherein said first ramp rate is different from said second ramp rate.

5. The method of operating an array of semiconductor memory cells of claim 4, wherein said first ramp rate is lower than said second ramp rate.

6. A method of operating an array of semiconductor memory cells, the array comprising a plurality of said semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising:

a floating body region configured to be charged to a level indicative of a state of the memory cell; and

a buried well region contacting said floating body region;

said method comprising;

selecting at least one of said at least one column or at least one row; and

selecting at least one of said buried well regions; and

disabling at least one of said plurality of said semiconductor cells not located in the at least one column or at least one row having been selected;

wherein said disabling comprises removing a bias from said buried well region contacting said floating body region of said at least one of said plurality of said semiconductor cells not located in the at least one column or at least one row having been selected.

7. The method of claim 6, comprising maintaining a bias to said at least one of said buried well regions that was selected.

8. The method of claim 6, further comprising performing an operation on at least one of said semiconductor memory cells having been selected by said selecting.

9. The method of claim 6, further comprising applying a bias to said buried well region to maintain states of said semiconductor memory cells that have not been disabled.

10. The method of claim 6, further comprising applying a first ramp rate for reading said state of a memory cell, and a second ramp rate for writing said memory cell, wherein said first ramp rate is different from said second ramp rate.

11. The method of claim 10, wherein first ramp rate is lower than said second ramp rate.