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Memory device comprising electrically floating body transistor

  • US 10,115,451 B2
  • Filed: 09/21/2017
  • Issued: 10/30/2018
  • Est. Priority Date: 08/15/2014
  • Status: Active Grant
First Claim
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1. A method of operating an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising:

  • a plurality of said semiconductor memory cells arranged in at least one column and at least one row, each said semiconductor memory cell comprising;

    a floating body region configured to be charged to a level indicative of a state of the memory cell;

    a first region in electrical contact with said floating body region, located at a surface of said floating body region;

    a second region in electrical contact with said floating body region, located at a surface of said floating body region, spaced apart from said first region;

    a gate positioned between said first region and said second region; and

    a third region in electrical contact with said floating body region, located below said floating body region;

    said method comprising;

    selecting said third region of at least one of said semiconductor memory cells in at least one of said at least two memory sub-arrays; and

    operating said at least one of said memory sub-arrays independently of operation of a remainder of said at least two memory sub-arrays not selected.

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