One time accessible (OTA) non-volatile memory

• US 10,115,467 B2
• Filed: 09/25/2015
• Issued: 10/30/2018
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: Jonker LLC
• Original Assignee: Jonker LLC
• Inventors: Liu, David K. Y., Gross, John Nicholas
• Primary Examiner(s): King, Douglas
• Application Number:
  US14/865,971
• Publication Number:
  US 20160093395A1
• Time in Patent Office: 1,131 Days
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0059 Security or protection circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2013/0047 Read destroying or disturbing the data

Abstract

A programmable non-volatile memory device effectuates two different functions (read, erase (re-program)) during a single instruction or command. During a first phase of the command a cell state is determined by a memory controller circuit, and in a second phase of the same command the cell state is re-written. This implementation is useful for applications where it is desirable to permit one time access only of particular data/content.

Claims

1. A method of operating a floating gate based non-volatile memory cell device that operates to store a logic state based on a value of a charge physically present on the floating gate in a memory cell, such that a first amount of charge represents a first logical value, and a second amount of charge represents a second logical value, the improvement comprising:

a hybrid read operation that when effectuated;

i. reads the stored memory cell logic state during a first phase;

and

ii. erases the stored memory cell logic state during an immediately subsequent second phase;

iii. senses said stored memory cell logical state by at least one of;

     1) integrating a total charge flowing through the device during at least a portion of time of said hybrid read operation; and

/or

     2) detecting a change in current as a function of at least a portion of time of said hybrid read operation for said memory device;

wherein a threshold voltage of the floating gate based memory cell device is caused to increase during an entirety of said hybrid read operation;

further wherein a stored logic state of the non-volatile memory cell device can be read at most once before it is erased.

2. The method of claim 1 wherein the non-volatile memory (NVM) cell device is erased by storing electrons on the floating gate.

3. The method of claim 2 wherein electrons are added to the floating gate during said immediately subsequent second phase.

4. The method of claim 3 wherein said electrons are added by channel hot electron injection.

5. The method of claim 1 wherein only a single access to the memory cell is required to effectuate achieve both a read and erase operation.

6. The method of claim 1 where a differential pair sense amplifier is used to detect the content of the memory cell.

7. The method of claim 1 wherein a threshold voltage Vt of each memory cell in a memory array of the device is restored to an unprogrammed level after each read of the contents of such cell.

8. The method of claim 1 wherein said hybrid read operation is used in a computing device during playback of multimedia content including audio and/or video.

9. The method of claim 1 wherein said hybrid read operation is used in an electronic key reading device during identification of content on an electronic key.

10. The method of claim 1 wherein said hybrid read operation is used in an electronic ticket reading device during identification of content on an electronic ticket.

11. The method of claim 10 wherein said hybrid read operation causes email, photos and videos to be erased after a one time access.

12. The method of claim 11 wherein said buffering is done by a second memory coupled to and on the same integrated circuit as the floating gate based NVM memory device.

13. The method of claim 1 wherein said hybrid read operation is used in a mobile computing device during access of content on such device.

14. The method of claim 1 further including a step:

buffering said data after it is read to preserve it for a predetermined period.

15. The method of claim 1 wherein said hybrid read operation is used in a communications circuit for buffering receive and/or transmit data.

16. The method of claim 1 wherein said hybrid read operation is used in a temporary data cache circuit.

17. The method of claim 1 wherein the floating gate based non-volatile memory cell device does not require or use a separate erase immediately prior to programming of cells.

18. The method of claim 1 wherein separate accesses are made to the memory cell during i) and ii) to effectuate achieve both a read and erase operation.

19. The method of claim 1 wherein said sensing occurs over an entire hybrid read operation cycle.

20. A non-volatile floating gate based memory cell device that stores a logic state based on a value of a charge physically present on the floating gate, such that a first amount of charge represents a first logical value, and a second amount of charge represents a second logical value, the device comprising:

a memory array;

a read/write controller circuit adapted to receive and perform a single read command for a hybrid read operation occurring during a hybrid read operation cycle and during which;

i. a read operation of the stored memory cell logic state can be determined during a first phase of the single read command; and

ii. an erase operation of the stored memory cell logic state can be achieved during an immediately subsequent second phase of the single read command;

wherein said hybrid read operation including two different operations can be performed on a memory cell in the memory array during a single access;

iii. sensing of said stored memory cell logical state occurs by integrating a total charge flowing through the device during said hybrid read operation cycle;

wherein said sensing occurs over said entire hybrid read operation cycle;

further wherein a stored logic state of the non-volatile memory cell device can be read at most once before it is erased.

21. The device of claim 20 wherein a threshold voltage of the floating gate based memory cell device is caused to increase during an entirety of said single read access.

22. The device of claim 20 wherein a programming operation for new data of the floating gate based memory cell device does not have to be preceded by an erase operation.

23. A method of operating a floating gate based non-volatile memory cell device that operates to store a logic state based on a value of a charge physically present on the floating gate in a memory cell, such that a first amount of charge represents a first logical value, and a second amount of charge represents a second logical value, the improvement comprising:

a hybrid read operation that when effectuated during a hybrid read operation cycle;

i. reads the stored memory cell logic state during a first phase;

and

ii. erases the stored memory cell logic state during an immediately subsequent second phase;

iii. senses said stored memory cell logical state by integrating a total charge flowing through the device during said hybrid read operation cycle for said memory device;

wherein said sensing occurs over said entire hybrid read operation cycle;

further wherein a stored logic state of the non-volatile memory cell device can be read at most once before it is erased.

24. A non-volatile floating gate based memory cell device that stores a logic state based on a value of a charge physically present on the floating gate, such that a first amount of charge represents a first logical value, and a second amount of charge represents a second logical value, the device comprising:

a memory array;

a read/write controller circuit adapted to receive and perform a single hybrid read command for a hybrid read operation occurring during a hybrid read operation cycle and during which;

i. a read operation of the stored memory cell logic state can be determined during a first phase of the single read command; and

ii. an erase operation of the stored memory cell logic state can be achieved during an immediately subsequent second phase of the single read command;

wherein two different operations can be performed on a memory cell in the memory array during a single access;

iii. sensing of said stored memory cell logical state occurs by at least one of;

     1) integrating a total charge flowing through the device during at least a portion of time of said hybrid read operation; and

/or

     2) detecting a change in current as a function of at least a portion of time of said hybrid read operation for said memory device;

wherein a threshold voltage of the floating gate based memory cell device is

caused to increase during an entirety of said hybrid read operation cycle;

further wherein a stored logic state of the non-volatile memory cell device can be read at most once before it is erased.