Semiconductor devices comprising nitrogen-doped gate dielectric, and methods of forming semiconductor devices

• US 10,115,642 B2
• Filed: 02/09/2018
• Issued: 10/30/2018
• Est. Priority Date: 11/30/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Moriwaki, Yoshikazu
• Primary Examiner(s): Hossain, Moazzam
• Assistant Examiner(s): Kilpatrick, Warren H
• Application Number:
  US15/893,414
• Publication Number:
  US 20180174926A1
• Time in Patent Office: 263 Days
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material. The second transistors include a second gate electrode, a second nitrogen-doped gate dielectric layer and a second high-k material. The second nitrogen-doped gate dielectric layer is doped with nitrogen to a different peak concentration than the first nitrogen-doped gate dielectric layer. Some embodiments include methods of forming PMOS and NMOS transistors having nitrogen-doped gate dielectric material.

Claims

1. A method of forming a semiconductor device comprising:

forming a gate dielectric layer extending across a location of a channel region of a PMOS transistor and across a location of a channel region of an NMOS transistor;

doping a first region of the gate dielectric layer with nitrogen to a first concentration;

after doping the first region of the gate dielectric layer with the nitrogen to the first concentration, doping a second region of the gate dielectric layer with nitrogen to a second concentration different from the first concentration;

one of the nitrogen-doped first and second regions of the gate dielectric layer including a nitrogen-doped NMOS gate dielectric material over and in direct physical contact with the channel region location of the NMOS transistor, and the other of the nitrogen-doped first and second regions of the gate dielectric layer including a nitrogen-doped PMOS gate dielectric material over and in direct physical contact with the channel region location of the PMOS transistor; and

the nitrogen-doped NMOS gate dielectric material being doped to a higher concentration of nitrogen than the nitrogen-doped PMOS gate dielectric material.

2. The method of claim 1, wherein the gate dielectric layer comprises silicon oxide.

3. The method of claim 1, wherein the nitrogen-doped first region of the gate dielectric layer includes the nitrogen-doped PMOS gate dielectric material.

4. The method of claim 3, wherein the nitrogen doping of the first region of the gate dielectric layer is accomplished utilizing a blanket nitrogen implant which also dopes the nitrogen into the second region of the gate dielectric layer to the first concentration.

5. The method of claim 1, wherein the nitrogen-doped first region of the gate dielectric layer includes the nitrogen-doped NMOS gate dielectric material.

6. The method of claim 1, wherein the nitrogen concentration doped into the nitrogen-doped NMOS gate dielectric material is at least about 30% greater than the nitrogen concentration doped into the nitrogen-doped PMOS gate dielectric material.

7. The method of claim 1, comprising forming a PMOS gate over the nitrogen-doped PMOS gate dielectric material;

with the PMOS gate including a metal-containing composition spaced from the nitrogen-doped PMOS gate dielectric material by aluminum oxide and an additional oxide.

8. The method of claim 7, comprising forming an NMOS gate over the nitrogen-doped NMOS gate dielectric material;

with the NMOS gate including the metal-containing composition spaced from the nitrogen-doped NMOS gate dielectric material by the additional oxide and not having aluminum oxide between the nitrogen-doped NMOS gate dielectric material and the metal-containing composition.

9. The method of claim 8, wherein the additional oxide comprises hafnium oxide.

10. The method of claim 8, wherein the metal-containing composition is a metal nitride.

11. The method of claim 1 wherein the first region of the gate dielectric layer includes the nitrogen-doped NMOS gate dielectric, the method comprising:

prior to the doping of the first region of the gate dielectric layer with the nitrogen, forming a blocking mask over the second region of the gate dielectric layer;

the blocking mask comprising silicon dioxide over a first silicon-containing material;

the doping of the first region of the gate dielectric layer with the nitrogen being conducted while the blocking mask is over the second region of the gate dielectric layer, and forming the nitrogen-doped NMOS gate dielectric material;

after the doping of the first region of the gate dielectric layer with the nitrogen, forming a second mask over at least some of the first region of the gate dielectric layer;

the second mask comprising silicon dioxide over a second silicon-containing material;

the first and second silicon-containing materials being a same composition as one another;

simultaneously removing the blocking mask and the second mask to expose the nitrogen-doped first region of the gate dielectric layer and the second region of the gate dielectric layer; and

doping the exposed second region of the gate dielectric layer with nitrogen to form the nitrogen-doped PMOS gate dielectric material, the doping of the exposed second region of the gate dielectric layer being conducted with a blanket nitrogen implant that also provides additional nitrogen dopant into the exposed nitrogen-doped first region of the gate dielectric layer.

12. The method of claim 1, comprising:

after doping the first region of the gate dielectric layer with the nitrogen;

forming a blocking mask over at least some of the first region of the gate dielectric layer;

the blocking mask comprising silicon dioxide over a first silicon-containing material;

the doping of the second region of the gate dielectric layer with the nitrogen being conducted while the blocking mask is over said at least some of the first region of the gate dielectric layer;

after the doping of the second region of the gate dielectric layer with the nitrogen, forming a second mask over at least some of the second region of the gate dielectric layer;

the second mask comprising silicon dioxide over a second silicon-containing material;

the first and second silicon-containing materials being a same composition as one another; and

simultaneously removing the blocking mask and the second mask to expose the nitrogen-doped NMOS gate dielectric material and the nitrogen-doped PMOS gate dielectric material.

13. The method of claim 12 wherein the doping of the first region of the gate dielectric layer with the nitrogen is conducted while no blocking mask is over both of the first region of the gate dielectric layer and the second region of the gate dielectric layer.

14. The method of claim 12 wherein the simultaneous removal of the blocking mask and the second mask utilizes a wet etch of the silicon dioxide of the blocking mask and the second mask, followed by at least one of a dry etch and a wet etch of the first and second silicon-containing materials of the blocking mask and the second mask.

15. The method of claim 1, wherein an isolation region is between the channel region of the PMOS transistor and the channel region of the NMOS transistor, and wherein the gate dielectric layer is formed to extend across the isolation region.

16. The method of claim 15, wherein the nitrogen-doped first region includes a first portion extending over the isolation region, and wherein the nitrogen-doped second region includes a second portion extending over the isolation region.

17. The method of claim 16, wherein the first portion extends more than halfway across an upper surface of the isolation region.

18. The method of claim 16, comprising removing the first and second portions from over the isolation region.

19. A method of forming a semiconductor device comprising:

forming a gate dielectric material extending across a location of a channel region of a PMOS transistor and across a location of a channel region of an NMOS transistor;

doping the gate dielectric material across the channel region of the PMOS transistor with nitrogen to a first concentration, thereby forming a first nitrogen doped region in direct physical contact with the channel region of the PMOS transistor;

doping the gate dielectric material across the channel region of the NMOS transistor to a second concentration that is at least about 30% greater than the first concentration, thereby forming a second nitrogen doped region in direct physical contact with the channel region of the NMOS transistor;

forming a first oxide over the gate dielectric material;

forming a second oxide over the second oxide;

forming a metal-containing composition over the second oxide; and

wherein the PMOS transistor includes both the first oxide and the second oxide, and wherein the NMOS transistor comprises only the first oxide between the gate dielectric material and the metal-containing composition.

20. The method of claim 19 wherein the metal-containing composition is a metal nitride, the first oxide is hafnium oxide and the second oxide is aluminum oxide.