Semiconductor device

• US 10,115,684 B2
• Filed: 02/03/2017
• Issued: 10/30/2018
• Est. Priority Date: 09/29/2014
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Watanabe, Shinpei, Uchida, Shinichi, Maeda, Tadashi, Henmi, Kazuo
• Primary Examiner(s): Ahmad, Khaja
• Application Number:
  US15/424,059
• Publication Number:
  US 20170148751A1
• Time in Patent Office: 634 Days
• Field of Search: None
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 38/14 Inductive couplings for wireless supply or distribution of electric power using inductive coupling H02J50/10
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48245 the item being metallic
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92147 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/48 : Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49513 : having bonding material between chip and die pad
• CPC Class Codes: H01L 23/4952 : the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 24/00 : Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/162 : the devices being mounted on two or more different substrates
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3511 : Warping
• CPC Class Codes: H04B 5/26 : using coils
• CPC Class Codes: H04B 5/72 : for local intradevice communication

Abstract

A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.

Claims

1. A semiconductor device, comprising:

a first semiconductor chip comprising;

a first plurality of wiring layers;

a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers; and

a first resin film formed over the uppermost layer of the first plurality of the wiring layers, a thickness of the first resin film being uniform between the first coil and the first dummy wires, and over top surfaces of the first coil and the first dummy wires; and

a second semiconductor chip comprising;

a second plurality of wiring layers;

a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers; and

a second resin film formed over the uppermost layer of the second plurality of the wiring layers, a thickness of the second resin film being uniform between the second coil and the second dummy wires, and over top surfaces of the second coil and the second dummy wires,

wherein the first semiconductor chip and the second semiconductor chip face each other via an insulation sheet,

wherein the first dummy wires are isolated from each other,

wherein the second dummy wires are isolated from each other, and

wherein the first coil and the second coil are magnetically coupled with each other.

2. The semiconductor device according to claim 1, wherein the first semiconductor chip further comprises:

a first region in which the first coil and the first dummy wires are disposed; and

a second region in which the first bonding pad is disposed,

wherein the second semiconductor chip further comprises;

a third region in which the second coil and the second dummy wires are disposed; and

a fourth region in which the second bonding pad is disposed,

wherein the first region is overlapped with the third region in a plan view, and

wherein the second region is not overlapped with the fourth region in the plan view.

3. The semiconductor device according to claim 1, wherein the first dummy wires are located around the first coil, and the second dummy wires are located around the second coil.

4. The semiconductor device according to claim 3, wherein the first dummy wires are further located within the first coil, and the second dummy wires are further located within the second coil.

5. The semiconductor device according to claim 1,

wherein the insulation sheet comprises:

a first main surface bonded to the first resin film; and

a second main surface bonded to the second resin film.

11. The semiconductor device according to claim 1, wherein a bottom surface of the first resin film abuts upper surfaces of the first dummy wires.

12. The semiconductor device according to claim 1, wherein, in a plan view, the first dummy wires are located between the first coil and the second coil.

13. The semiconductor device according to claim 1, wherein the first dummy wires are located within and around the first coil.

14. The semiconductor device according to claim 13, wherein the second dummy wires are located within and around the second coil.

6. A semiconductor device, comprising:

a first semiconductor chip comprising;

a first plurality of wiring layers;

a first coil formed in the first plurality of the wiring layers;

a first bonding pad and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers; and

a first resin film formed over the uppermost layer of the first plurality of the wiring layers, a thickness of the first resin film being uniform between the first coil and the first dummy wires, and over top surfaces of the first coil and the first dummy wires; and

a second semiconductor chip comprising;

a second plurality of wiring layers;

a second coil formed in the second plurality of the wiring layers; and

a second bonding pad and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers; and

a second resin film formed over the uppermost layer of the second plurality of the wiring layers, a thickness of the second resin film being uniform between the second coil and the second dummy wires, and over top surfaces of the second coil and the second dummy wires,

wherein the first semiconductor chip and the second semiconductor chip face each other via an insulation sheet,

wherein the first dummy wires are isolated from each other,

wherein the second dummy wires are isolated from each other, and

wherein the first coil and the second coil are magnetically coupled with each other.

7. The semiconductor device according to claim 6, wherein the first semiconductor chip further comprises:

a first region in which the first coil and the first dummy wires are disposed; and

a second region in which the first bonding pad is disposed;

wherein the second semiconductor chip further comprises;

a third region in which the second coil and the second dummy wires are disposed; and

a fourth region in which the second bonding pad is disposed,

wherein the first region is overlapped with the third region in a plan view, and

wherein the second region is not overlapped with the fourth region in a plan view.

8. The semiconductor device according to claim 6, wherein the first dummy wires are located around the first coil, and the second dummy wires are located around the second coil.

9. The semiconductor device according to claim 8, wherein the first dummy wires are further located within the first coil, and the second dummy wires are further located within the second coil.

10. The semiconductor device according to claim 6,

wherein the insulation sheet comprises:

a first main surface bonded to the first resin film; and

a second main surface bonded to the second resin film.

15. The semiconductor device according to claim 6, wherein a bottom surface of the first resin film abuts upper surfaces of the first dummy wires.

16. The semiconductor device according to claim 6, wherein, in a plan view, the first dummy wires are located between the first coil and the second coil.

17. The semiconductor device according to claim 6, wherein the first dummy wires are located within and around the first coil.

18. The semiconductor device according to claim 17, wherein the second dummy wires are located within and around the second coil.