Three-dimensional memory device containing structurally reinforced pedestal channel portions and method of making thereof

• US 10,115,730 B1
• Filed: 06/19/2017
• Issued: 10/30/2018
• Est. Priority Date: 06/19/2017
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Baraskar, Ashish, Hosoda, Naohiro, Zhang, Yanli, Makala, Raghuveer S., Tanaka, Hiroyuki, Nakamura, Ryo, Nakamura, Tadashi
• Primary Examiner(s): Ahmed, Selim
• Application Number:
  US15/626,766
• Time in Patent Office: 498 Days
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a semiconductor surface, a memory opening extending through the alternating stack, a semiconductor pedestal channel portion located at a bottom portion of the memory opening and contacting a top surface of the semiconductor surface, and a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion. The memory stack structure includes a memory film and a vertical semiconductor channel located inside the memory film. A maximum lateral extent of the pedestal channel portion is greater than a maximum lateral dimension of an entire interface between the pedestal channel portion and the memory stack structure.

Claims

1. A three-dimensional memory device comprising:

an alternating stack of insulating layers and electrically conductive layers located over a semiconductor surface;

a memory opening extending through the alternating stack;

a pedestal channel portion located at a bottom portion of the memory opening, comprising a semiconductor material, and contacting a top surface of the semiconductor surface; and

a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion, wherein the memory stack structure comprises a memory film and a vertical semiconductor channel located inside the memory film,

wherein;

a maximum lateral extent of the pedestal channel portion is greater than a maximum lateral dimension of an entire interface between the pedestal channel portion and the memory stack structure, the entire interface includes all surfaces at which the pedestal channel portion directly contacts the memory stack structure; and

the maximum lateral extent of the pedestal channel portion is provided above a horizontal plane including a top surface of the bottommost electrically conductive layer among the electrically conductive layers or below a horizontal plane including a bottom surface of a bottommost electrically conductive layer.

2. The three-dimensional memory device of claim 1, further comprising an annular silicon oxide spacer contacting, and laterally surrounding, the pedestal channel portion, and laterally surrounded by the bottommost electrically conductive layer.

3. The three-dimensional memory device of claim 2, wherein the maximum lateral extent of the pedestal channel portion is a lateral separation distance between portions of an interface between the pedestal channel portion and the annular silicon oxide spacer.

4. The three-dimensional memory device of claim 2, wherein an entire inner sidewall of the annular silicon oxide spacer is located outside a cylindrical vertical plane including a periphery of the entire interface between the pedestal channel portion and the memory stack structure.

5. The three-dimensional memory device of claim 1, wherein an interface between the semiconductor surface and the pedestal channel portion includes a cylindrical sidewall having a maximum lateral dimension that is greater than the maximum lateral dimension of the entire interface between the pedestal channel portion and the memory stack structure.

6. The three-dimensional memory device of claim 5, wherein the maximum lateral extent of the pedestal channel portion is the maximum lateral dimension of the cylindrical sidewall.

7. The three-dimensional memory device of claim 1, further comprising a gate dielectric layer located between the semiconductor surface and the bottommost electrically conductive layer, wherein an interface between the gate dielectric layer and the pedestal channel portion that includes all surfaces at which the gate dielectric layer directly contacts the pedestal channel portion has a maximum lateral dimension that is greater than the maximum lateral dimension of the entire interface between the pedestal channel portion and the memory stack structure.

8. The three-dimensional memory device of claim 1, wherein the semiconductor surface comprises a surface of a substrate or a surface of a semiconductor material layer located over a substrate.

9. The three-dimensional memory device of claim 8, wherein:

the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;

the substrate comprises a silicon substrate;

the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

10. The three-dimensional memory device of claim 1, wherein the entire interface includes:

an annular horizontal surface at which the memory film directly contacts a topmost surface of the pedestal channel portion;

a vertical cylindrical surface at which the vertical semiconductor channel directly contacts a cylindrical sidewall of the pedestal channel portion; and

a horizontal surface at which the vertical semiconductor channel directly contacts a recessed top surface of the pedestal channel portion.

11. The three-dimensional memory device of claim 10, wherein the entire interface consists of the annular horizontal surface, the vertical cylindrical surface, and the horizontal surface.

12. The three-dimensional memory device of claim 10, wherein an entire outer periphery of the annular horizontal surface directly contacts one of the insulating layers that overlie the bottommost electrically conductive layer.

13. The three-dimensional memory device of claim 1, wherein a horizontal surface of the pedestal channel portion contacts a horizontal bottom surface of an insulating layer that overlies the bottommost electrically conductive layer.

14. The three-dimensional memory device of claim 13, wherein a convex surface of the pedestal channel portion contacts a concave surface of the insulating layer that overlies the bottommost electrically conductive layer.

15. The three-dimensional memory device of claim 13, wherein a portion of the gate dielectric layer underlying a peripheral portion of the pedestal channel portion has a lesser vertical thickness than a portion of the gate dielectric layer that underlies the bottommost electrically conductive layer.

16. The three-dimensional memory device of claim 1, wherein a region of the pedestal channel portion directly contacts a portion of the bottom surface of the gate dielectric layer.

17. The three-dimensional memory device of claim 1, wherein a region of the pedestal channel portion directly contacts a portion of the top surface of the gate dielectric layer.

18. The three-dimensional memory device of claim 1, wherein:

the memory stack structure is located in a memory opening;

the pedestal channel portion contains a protruding part;

the maximum lateral extent of the pedestal channel portion is located in the protruding part;

the maximum lateral extent of the pedestal channel portion is greater than the maximum lateral dimension of the memory opening; and

the protruding part of the pedestal channel portion laterally protrudes past the memory stack structure located in the memory opening.