Process method and structure for high voltage MOSFETs

• US 10,115,814 B2
• Filed: 01/19/2018
• Issued: 10/30/2018
• Est. Priority Date: 05/10/2013
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Ding, Yongping, Zhang, Lei, Chang, Hong, Kim, Jongoh, Chen, John
• Primary Examiner(s): Yechuri, Sitaramarao S
• Application Number:
  US15/875,932
• Publication Number:
  US 20180145167A1
• Time in Patent Office: 284 Days
• Field of Search: None
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.

Claims

1. A method for manufacturing a semiconductor power device on a semiconductor substrate comprising:

depositing a hard mask atop the semiconductor substrate and patterning the hard mask according to a pre-determined trench configuration;

etching the semiconductor substrate through the patterned hard mask to form a plurality of trenches in the top portion of the semiconductor substrate each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench with the endpoint sidewall extends vertically downward from a top surface to a trench bottom surface;

applying vertical high energy implant to form trench bottom dopant regions below the trench bottom surface followed by removing the hard mask;

depositing an insulation layer for covering trench sidewalls and an insulation layer for covering the trench bottom surfaces;

applying a low energy tilt implant to form a sidewall dopant region along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region to pick-up the trench bottom dopant region to the top surface of the semiconductor substrate; and

forming at least two of the endpoint sidewall body dopant regions in at least two of the endpoint sidewalls that are immediately adjacent to each other as adjacent endpoint sidewall body dopant regions with the adjacent endpoint sidewall body dopant regions extend through an entire semiconductor region between at least two of the endpoint sidewalls and merging the adjacent endpoint sidewall body dopant regions into a joined endpoint sidewall body dopant region to extend vertically downward along an entire length of the endpoint sidewalls of the adjacent trenches to reach and directly contact the laterally extended region of the trench bottom body dopant region.

2. The method of claim 1 wherein

the step of depositing the insulation for covering the trench sidewalls and the trench bottom surfaces further comprising a step of depositing the insulation layer covering the trench sidewalls and the insulation layer covering the trench bottom surfaces have approximately a same thickness.

3. The method of claim 1 wherein:

the step of depositing the insulation for covering the trench sidewalls and the trench bottom surfaces further comprising a step of depositing the insulation layer covering the trench sidewalls has a smaller layer thickness than the insulation layer covering the trench bottom surface.

4. The method of claim 1 wherein:

the step etching the semiconductor substrate through the patterned hard mask to form a plurality of trenches in the top portion of the semiconductor further comprising a step of forming each trench to extend between two pre-designated locations with the trenches have different lengths.

5. The method of claim 1 wherein:

the step etching the semiconductor substrate through the patterned hard mask to form a plurality of trenches in the top portion of the semiconductor further comprising a step of forming each trench to extend between two pre-designated locations with the trenches have different lengths and wherein the trench endpoints are distributed at the designated locations on the entire surface of the semiconductor substrate.

6. The method of claim 1 further comprising:

manufacturing the semiconductor power device as a high voltage (HV) MOSFET device.

7. The method of claim 1 further comprising:

manufacturing the semiconductor power device as a high voltage (HV) IGBT.