Transistor structures having a deep recessed P+ junction and methods for making same

• US 10,115,815 B2
• Filed: 12/28/2012
• Issued: 10/30/2018
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Zhang, Qingchun, Hull, Brett
• Primary Examiner(s): Yechuri, Sitaramarao S
• Application Number:
  US13/730,068
• Publication Number:
  US 20140183552A1
• Time in Patent Office: 2,132 Days
• Field of Search: 257 77
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SIC) MOSFET device.

Claims

1. A transistor device comprising:

a gate and a source on an upper surface of the transistor device;

at least one doped well region of a first conductivity type that is different from a second conductivity type of a source region within the transistor device, the at least one doped well region having a recessed portion below the source and extending from the at least one doped well region by a depth sufficient to reduce an electrical field on a gate oxide on the gate, the recessed portion having a doping concentration that is less than a doping concentration of the at least one doped well region; and

a termination area adjacent the at least one doped well region, the termination area including at least one termination structure adjacent the at least one doped well region where the recessed portion is recessed deeper than the termination structure.

2. The transistor device according to claim 1, wherein a body of the transistor device comprises silicon carbide.

3. The transistor device according to claim 1, wherein the at least one doped well region is a P+ implanted junction.

4. The transistor device according to claim 1, wherein the at least one doped well region is in a source contact area of the transistor device.

5. The transistor device according to claim 1, wherein the depth is sufficient to result in an avalanche path to occur wholly within an active area of the transistor device instead of a termination device.

6. The transistor device according to claim 1, wherein the depth is about approximately 0.7 microns to about approximately 1.5 microns.

7. The transistor device according to claim 1, wherein the depth is about approximately 0.7 microns to about approximately 0.9 microns.

8. The transistor device according to claim 1, wherein the depth is about approximately 0.9 microns to about approximately 1.1 microns.

9. The transistor device according to claim 1, wherein the depth is about approximately 1.1 microns to about approximately 1.3 microns.

10. The transistor device according to claim 1, wherein the transistor device is an MOSFET.

11. The transistor device according to claim 1, wherein the transistor device is an insulated gate bipolar transistor.

12. The transistor device according to claim 1, wherein the transistor device is a metal-oxide-semiconductor controlled thyristor.

13. The transistor device according to claim 1, wherein the first conductivity type is P+, and the second conductivity type is N+.

14. The transistor device according to claim 1, comprising at least one sidewall wherein at least a portion of the upper surface and the sidewall of the transistor device is etched away to a recess depth as measured from the upper surface.

15. The transistor device according to claim 14, wherein at least a portion of the source region is etched away.

16. The transistor device according to claim 14, wherein at least a portion of the at least one doped well region is etched away.

17. The transistor device according to claim 14, wherein the recess depth is about approximately 0.2 microns to about approximately 1.0 microns.

18. The transistor device according to claim 14, wherein the recess depth is about approximately 0.2 microns to about approximately 0.4 microns.

19. The transistor device according to claim 14, wherein the recess depth is about approximately 0.4 microns to about approximately 0.6 microns.

20. The transistor device according to claim 14, wherein a large ohmic contact area is formed in an area of the source region when the at least a portion of the upper surface and the sidewall of the transistor device is etched away to the recess depth.