Reducing MOSFET body current

• US 10,115,818 B1
• Filed: 01/15/2018
• Issued: 10/30/2018
• Est. Priority Date: 08/23/2017
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Eggermont, Jean-Paul, Janssens, Johan Camiel Julia
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US15/871,231
• Time in Patent Office: 288 Days
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7826 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0009 AC switches, i.e. delivering AC power to a load
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 2217/0027 Measuring means of, e.g. currents through or voltages across the switch

Abstract

An illustrative bidirectional MOSFET switch includes a body region, a buried layer, a gate terminal, a first configuration switch, and a second configuration switch. The body region is a semiconductor of a first type separating a source region and a drain region that are a semiconductor of a second type. The buried layer is a semiconductor of the second type separating the body region from a substrate that is a semiconductor of the first type. The gate terminal is drivable to form a channel in the body region, thereby enabling conduction between the source terminal and the drain terminal. The first configuration switch disconnects the body terminal from the source terminal when the source terminal voltage exceeds the drain terminal voltage; and the second configuration switch connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage.

Claims

1. A bidirectional MOSFET switch having reduced body current, the switch comprising:

a body region that is a semiconductor of a first type separating a source region and a drain region that are a semiconductor of a second type, the body region being connected to a body terminal, the source region being connected to a source terminal, and the drain region being connected to a drain terminal;

a buried layer that is a semiconductor of the second type separating the body region from a substrate that is a semiconductor of the first type, the buried layer being coupled to a buried layer terminal;

a gate terminal drivable to form a channel in the body region, thereby enabling conduction between the source terminal and the drain terminal;

a first configuration switch that disconnects the body terminal from the source terminal when the source terminal voltage exceeds the drain terminal voltage; and

a second configuration switch that connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage.

2. The switch of claim 1, wherein the first type of semiconductor is N-type, and the second type of semiconductor is P-type.

3. The switch of claim 1, wherein the first type of semiconductor is P-type, and the second type of semiconductor is N-type.

4. The switch of claim 3, wherein the first configuration switch disconnects the body terminal from the source terminal when the source terminal voltage exceeds the drain terminal voltage unless the gate terminal is de-asserted, and the second configuration switch connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage unless the gate terminal is de-asserted.

5. The switch of claim 4, wherein the first configuration switch connects the body terminal to the source terminal when the drain terminal voltage exceeds the source terminal voltage or the gate terminal is de-asserted, and the second configuration switch disconnects the body terminal from the buried layer terminal when the drain terminal voltage exceeds the source terminal voltage or the gate terminal is de-asserted.

6. The switch of claim 3, wherein the first configuration switch connects the body terminal to the source terminal when the drain terminal voltage exceeds the source terminal voltage, and the second configuration switch disconnects the body terminal from the buried layer terminal when the drain terminal voltage exceeds the source terminal voltage.

7. The switch of claim 6, wherein the buried layer floats while disconnected by the second configuration switch.

8. The switch of claim 3, wherein the first and second configuration switches each comprise an NMOS transistor.

9. The switch of claim 8, wherein the first and second configuration switches each have a body terminal coupled to the MOSFET switch'"'"'s source terminal regardless of whether the source terminal voltage exceeds the drain terminal voltage.

10. The switch of claim 3, wherein the first and second configuration switches each comprise an anti-series pair of NMOS transistors.

11. The switch of claim 1, further comprising a switch controller that drives the first and second configuration switches based at least in part on the drain terminal voltage and the source terminal voltage.

12. The switch of claim 11, wherein the switch controller'"'"'s driving of the first and second configuration switches is further based on whether the gate terminal is asserted.

13. The switch of claim 1, further comprising a first sense transistor coupled between the source terminal and a drain current sensing terminal and a second sense transistor coupled between the drain terminal and a source current sensing terminal, wherein the MOSFET switch monitors forward current using at least the drain current sensing terminal and monitors reverse current using at least the source current sensing terminal.

14. A method of manufacturing a bidirectional MOSFET switch having reduced body current, the method comprising:

creating an n-type buried layer underlying a p-type body region;

forming in the body region an n-type source region and an n-type drain region;

connecting a buried layer terminal to the buried layer, a body terminal to the body region, a source terminal to the source region, and a drain terminal to the drain region;

providing a gate terminal that is drivable to form a channel in the body region, thereby enabling conduction between the source terminal and the drain terminal;

coupling a first configuration switch between the body terminal and the source terminal to disconnect the body terminal from the source terminal when the source terminal voltage exceeds the drain terminal voltage; and

coupling a second configuration switch between the body terminal and buried layer terminal to connect the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage.

15. The method of claim 14, wherein the first configuration switch disconnects the body terminal from the source terminal when the source terminal voltage exceeds the drain terminal voltage unless the gate terminal is de-asserted, and the second configuration switch connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage unless the gate terminal is de-asserted;

and wherein the first configuration switch connects the body terminal to the source terminal when the drain terminal voltage exceeds the source terminal voltage or the gate terminal is de-asserted, and the second configuration switch disconnects the body terminal from the buried layer terminal when the drain terminal voltage exceeds the source terminal voltage or the gate terminal is de-asserted.

16. The method of claim 14, wherein the first configuration switch connects the body terminal to the source terminal when the drain terminal voltage exceeds the source terminal voltage, and the second configuration switch disconnects the body terminal from the buried layer terminal when the drain terminal voltage exceeds the source terminal voltage.

17. The method of claim 14, wherein the buried layer floats while disconnected by the second configuration switch.

18. The method of claim 14, wherein the first and second configuration switches each comprise an NMOS transistor, and the method further comprises connecting the source terminal to a body region of each of the first and second configuration switches.

19. The method of claim 14, further comprising:

furnishing the switch with a controller that drives the first and second configuration switches based at least in part on the drain terminal voltage and the source terminal voltage.

20. The method of claim 19, wherein the controller'"'"'s driving of the first and second configuration switches is further based on whether the gate terminal is asserted.

21. The method of claim 14, further comprising:

deriving a forward current sense signal with a first sense transistor coupled to the source terminal and gate terminal; and

deriving a reverse current sense signal with a second sense transistor coupled to the drain terminal and the gate terminal.