Power converter with adaptive zero-crossing current detection

• US 10,116,211 B2
• Filed: 10/28/2015
• Issued: 10/30/2018
• Est. Priority Date: 02/11/2015
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Chen, Yung Hsu, Chu, Kuan-Yu
• Primary Examiner(s): Berhane, Adolf
• Application Number:
  US14/924,910
• Publication Number:
  US 20160233771A1
• Time in Patent Office: 1,098 Days
• Field of Search: 323271, 323282-286
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/0048 Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A power converter with adaptive zero-crossing current detection is provided. The power converter includes a first transistor, a second transistor, a PWM (Pulse Width Modulation) controller, a low-pass filter, and a delay controller. The first transistor is coupled between a supply voltage and a common node. The second transistor is coupled between the common node and a ground voltage. The common node has a reactive voltage. A reactive current flows through the common node. The PWM controller selectively enables and disables the first transistor and the second transistor according to a second control signal and a first transistor control signal. The low-pass filter is coupled between the common node and an output node. The delay controller generates the second control signal according to the reactive voltage.

Claims

1. A power converter, comprising:

a first transistor, coupled between a VDD supply voltage and a common node;

a second transistor, coupled between the common node and a ground voltage, wherein the common node has a reactive voltage, and a reactive current flows through the common node;

a PWM (Pulse Width Modulation) controller, selectively enabling and disabling the first transistor and the second transistor according to a second control signal and a first transistor control signal;

a low-pass filter, coupled between the common node and an output node; and

a delay controller, generating the second control signal according to a first control signal, wherein the delay controller comprises;

a first comparator, comparing the reactive voltage with a reference voltage so as to generate the first control signal; and

a delay unit directly connected to an output of the first compactor, directly delaying the first control signal for a first delay time so as to generate the second control signal.

2. The power converter as claimed in claim 1, wherein the first transistor is a PMOS transistor (P-type Metal Oxide Semiconductor Field Effect Transistor), and the second transistor is an NMOS transistor (N-type Metal Oxide Semiconductor Field Effect Transistor).

3. The power converter as claimed in claim 1, wherein the PWM controller comprises:

a pre-driver, driving the first transistor and the second transistor; and

a PWM logic circuit, controlling the pre-driver according to the second control signal.

4. The power converter as claimed in claim 1, wherein the low-pass filter comprises:

an inductor, coupled between the common node and the output node; and

a capacitor, coupled between the output node and the ground voltage.

5. The power converter as claimed in claim 1, wherein in a first operation state, the first transistor and the second transistor are both disabled, such that the reactive voltage is kept at a previous output voltage, and the reactive current is kept at zero.

6. The power converter as claimed in claim 5, wherein in a second operation state, the first transistor is enabled and the second transistor is disabled, such that the reactive voltage immediately rises from the previous output voltage to the supply voltage, and the reactive current gradually increases from zero to a maximum value.

7. The power converter as claimed in claim 1, wherein the delay unit further delays the second control signal for a second delay time so as to generate a third control signal, and further delays the third control signal for a third delay time so as to generate a fourth control signal.

8. The power converter as claimed in claim 1, wherein the first delay time is adjustable.

9. The power converter as claimed in claim 8, wherein the delay unit is controlled to continuously increase the first delay time until signals within the delay unit satisfies a condition, so as to determine an optimized value of the first delay time.

10. The power converter as claimed in claim 7, wherein the first delay time is adjustable, and the second delay time and the third delay time are predetermined.

11. The power converter as claimed in claim 10, wherein the delay controller further comprises:

a second comparator, comparing the reactive voltage with the ground voltage so as to generate an evaluation signal.

12. A power converter, comprising:

a first transistor, coupled between a supply voltage and a common node;

a second transistor, coupled between the common node and a ground voltage, wherein the common node has a reactive voltage, and a reactive current flows through the common node;

a PWM (Pulse Width Modulation) controller, selectively enabling and disabling the first transistor and the second transistor according to a second control signal and a first transistor control signal;

a low-pass filter, coupled between the common node and an output node; and

a delay controller, generating the second control signal according to the first control signal, wherein the delay controller comprises;

a first comparator, comparing the reactive voltage with a reference voltage so as to generate a first control signal;

a delay unit, delaying the first control signal for a first delay time so as to generate the second control signal, wherein the delay unit further delays the second control signal for a second delay time so as to generate a third control signal, and further delays the third control signal for a third delay time so as to generate a fourth control signal, wherein the first delay time is adjustable, and the second delay time and the third delay time are predetermined;

a second comparator, comparing the reactive voltage with the ground voltage so as to generate an evaluation signal; and

a sampling unit, sampling the evaluation signal at a transition edge of the third control signal so as to generate a first digital signal, and sampling the evaluation signal at a transition edge of the fourth control signal so as to generate a second digital signal.

13. The power converter as claimed in claim 12, wherein the delay controller further comprises:

a sequential counter, selectively increasing a digital number according to the first digital signal and the second digital signal.

14. The power converter as claimed in claim 13, wherein the sequential counter keeps increasing the digital number until the first digital signal and the second digital signal have different logic levels.

15. The power converter as claimed in claim 13, wherein the delay unit adjusts the first delay time in proportion to the digital number.

16. The power converter as claimed in claim 13, wherein if the first digital signal and the second digital signal have different logic levels, it represents that the first delay time has been optimized, and the second transistor is disabled at a specific time when the reactive current substantially reaches to zero.

17. A power converter, comprising:

a first transistor, coupled between a supply voltage and a common node;

a second transistor, coupled between the common node and a ground voltage, wherein the common node has a reactive voltage, and a reactive current flows through the common node;

a PWM (Pulse Width Modulation) controller, selectively enabling and disabling the first transistor and the second transistor according to a second control signal and a first transistor control signal;

a low-pass filter, coupled between the common node and an output node; and

a delay controller, generating the second control signal according to the first control signal;

wherein in a first operation state, the first transistor and the second transistor are both disabled, such that the reactive voltage is kept at a previous output voltage, and the reactive current is kept at zero,

wherein in a second operation state, the first transistor is enabled and the second transistor is disabled, such that the reactive voltage immediately rises from the previous output voltage to the supply voltage, and the reactive current gradually increases from zero to a maximum value;

wherein in a third operation state, the first transistor is disabled and the second transistor is enabled, such that the reactive voltage immediately falls from the supply voltage to a negative voltage and then gradually rises from the negative voltage, and the reactive current gradually decreases from the maximum value.

18. The power converter as claimed in claim 17, wherein the second transistor is disabled at a transition edge of the second control signal, thereby terminating the third operation state.

19. The power converter as claimed in claim 18, wherein in a fourth operation state, the first transistor and the second transistor are both disabled, such that an additional current path is formed by a body diode of the second transistor, and the reactive current flows through the additional current path and gradually decreases to zero.

20. The power converter as claimed in claim 19, wherein after the reactive current decreases to zero, the reactive voltage starts to oscillate up.