Ultrasonic control system and method for a buck-boost power converter

• US 10,116,216 B2
• Filed: 03/29/2016
• Issued: 10/30/2018
• Est. Priority Date: 03/29/2016
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Park, Jinseok, Zou, Han, Patel, Kedar Bharat
• Primary Examiner(s): Benitez, Gustavo Rosario
• Assistant Examiner(s): Rivera-Perez, Carlos
• Application Number:
  US15/084,345
• Publication Number:
  US 20170288550A1
• Time in Patent Office: 945 Days
• Field of Search: 323205-211, 323222-226, 323259, 323271-277, 323282-286, 323351, 363 65, 363123-127
• CPC Class Codes: H02M 1/14 Arrangements for reducing ripples from dc input or output
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence

Abstract

An embodiment of a buck-boost power converter may include an inductor driver section configured to control four switches to control an output of the converter, and a PWM circuit to generate a PWM control signal responsive to an output level of the output. An embodiment of a switch control is configured to, when an on time of the second switch becomes less than a specified entry value, force the third switch to generate boot refreshing pulses with an on time of a specified duration value at a rate more than a specified frequency, and when an on time of the third switch becomes less than the specified entry value, force the second switch to generate boot refreshing pulses with an on time of the specified duration value at the rate more than the specified frequency.

Claims

1. A circuit for a buck-boost power converter comprising:

an inductor driver comprising a first switch to selectively couple an input to a first node of an inductor, a second switch to selectively couple the first node of the inductor to a ground node, a third switch to selectively couple a second node of the inductor to the ground node, and a fourth switch to selectively couple the second node of the inductor to an output;

a pulse width modulator (PWM) to generate a PWM control signal responsive to an output level of the output;

a switch control in communication with the second switch and the third switch;

the circuit configured to operate in a buck mode with the fourth switch enabled for the buck mode and to begin to transition to a boost mode wherein the switch control is configured to, during the transition to the boost mode, detect an on time of the third switch less than a specified entry value and force the second switch to generate first boot refreshing pulses so that the second switch is enabled, during an on-time of the third switch, with an on time of a specified duration value at a rate more than a specified frequency, the circuit configured to subsequently operate in the boost mode after generation of the first boot refreshing pulses;

the circuit configured to operate in the boost mode with the first switch enabled for the boost mode and to begin to transition to the buck mode wherein the switch control is configured to, during the transition to the buck mode, detect on time of the second switch less than the specified entry value and force the third switch to generate second boot refreshing pulses so that the third switch is enabled, during an on time of the second switch, with an on time of the specified duration value at a rate more than the specified frequency, the circuit configured to subsequently operate in the buck mode after generation of the second boot refreshing pulses.

2. The circuit of claim 1, wherein, when the switch control is generating the first or second boot refreshing pulses, and when the on time of the second switch or the third switch becomes greater than a specified exit value, cease generating the first or second boot refreshing pulses.

3. The circuit of claim 2, wherein the specified exit value is greater than the specified entry value.

4. The circuit of claim 2, wherein the specified exit value is essentially equal to the specified entry value.

5. The circuit of claim 1, wherein the specified duration value is selected so that a frequency of the PWM control signal is maintained above 20 Kilohertz.

6. The circuit of claim 1, wherein the switch control is configured to, when the on time of the second switch becomes less thane a first specified entry value for a specified successive quantity of times, force the third switch to generate the second boot refreshing pulses at the rate more than the specified frequency, and when the on time of the third switch becomes less than a third specified entry value for the specified successive quantity of times, force the second switch to generate the first boot refreshing pulses at the rate more than the specified frequency.

7. The circuit of claim 6, wherein the switch control comprises circuitry to enable setting of at least one of the specified entry value, a specified exit value, and the specified successive quantity of times following manufacture of the switch control section.

8. The circuit of claim 1, wherein the PWM comprises a dual edge current programmed mode control (DECPM) controller.

9. The circuit of claim 1, wherein the specified frequency comprises an audible frequency level.

10. A method of forming a circuit for buck-boost control comprising:

providing an inductor driver comprising a first switch to selectively couple an input to a first node of an inductor, a second switch to selectively couple the first node of the inductor to a ground node, a third switch to selectively couple a second node of the inductor to the ground node, and a fourth switch to selectively couple the second node of the inductor to an output, and a pulse width modulator (PWM) to generate a PWM control signal responsive to an output level of the output; and

configuring an error section of the circuit to form a compensation signal that is representative of a deviation of the output level;

configuring the PWM section to form a first ramp and a second ramp wherein the second ramp is complementary to the first ramp so that a peak of the first ramp occurs at a valley of the second ramp and wherein the first ramp crosses the second ramp substantially at a midpoint wherein a dead zone is a region around the midpoint;

configuring the circuit to operate in a buck mode in response to the compensation signal having a value of one of greater than or less than the dead zone and to operate in a boost mode in response to the compensation signal being an opposite of one of greater than or less than the dead zone;

configuring the circuit to transition from the buck mode to the boost mode in response to the compensation signal entering the dead zone wherein in response to detecting an on time of the third switch less than a specified entry value during the transition from the buck mode to the boost mode, force the second switch to generate first boot refreshing pulses which enable the second switch, during an on time of the third switch, with an on time of a specified duration value at the rate more than a specified frequency to move the compensation signal outside the dead zone, and wherein the circuit is configured to operate in the boost mode after generating the first boot pulses; and

configuring the circuit to transition from the boost mode to the buck mode in response to the compensation signal entering the dead zone wherein in response to detecting an on time of the second switch less than the specified entry value during the transition from the boost mode to the buck mode, force the third switch to generate second boot refreshing pulses to enable the third switch, during an on time of the second switch, with an on time of the specified duration value at the rate more than the specified frequency.

11. The method of claim 10, further comprising configuring a switch control to, when the switch control is generating the first or second boot refreshing pulses and when the on time of the second switch or the third switch becomes greater than a specified exit value, cease generating the first or second boot refreshing pulses.

12. The method of claim 11, including configuring the switch control with the specified exit value greater than the specified entry value.

13. The method of claim 11, including configuring the switch control with the specified exit value essentially equal to the specified entry value.

14. The method of claim 10, further comprising selecting the specified duration value so that a frequency of the PWM control signal is maintained above 20 Kilohertz.

15. The method of claim 10, further comprising

configuring a switch control to:

when the on time of the second switch becomes less than a first specified entry value for a specified successive quantity of times, force the third switch to generate the second boot refreshing pulses at the rate more than the specified frequency; and

when the on time of the third switch becomes less than a third specified entry value for the specified successive quantity of times, force the second switch to generate the first boot refreshing pulses at the rate more than the specified frequency.

16. The method of claim 15, further comprising setting at least one of the specified entry value, a specified exit value, and the specified successive quantity of times following manufacture of the switch control section.

17. The method of claim 10, including configuring the PWM to include a dual edge current programmed mode control (DECPM) controller.

18. The method of claim 10 including configuring the PWM section to form the first ramp and the second ramp with substantially equal amplitudes.

19. A buck-boost power converter comprising:

an inductor driver comprising a first switch to selectively couple an input to a first node of an inductor, a second switch to selectively couple the first node of the inductor to a ground node, a third switch to selectively couple a second node of the inductor to the ground node, and a fourth switch to selectively couple the second node of the inductor to an output;

a pulse width modulator (PWM) to generate a PWM control signal responsive to an output level of the output, the PWM configured to form two complementary ramp signals that cross at substantially a midpoint and having a dead zone around the midpoint, the PWM configured to operate in a buck mode and a boost mode and to transition therebetween; and

a switch control to;

in response to an on time of the second switch less than a specified entry value for a specified quantity of times after exiting the boost mode and beginning a first transition to the buck mode, force the third switch to generate first boot refreshing pulses to enable the third switch, during an on time of the second switch, with an on time of a specified duration value at the rate more than a specified frequency wherein the PWM operates in the buck mode after completing the first boot refreshing pulses; and

in response to an on time of the third switch less than the specified entry value, for the specified quantity of times after exiting the buck mode and beginning a second transition to the boost mode, force the second switch to generate second boot refreshing pulses to enable the second switch, during an on time of the third switch, with an on time of the specified duration value at the rate more than the specified frequency wherein the PWM operates in the boost mode after completing the second boot refreshing pulses;

when the switch control is generating the first or second boot refreshing pulses and the on time of the second switch or the third switch becomes greater than a specified exit value, cease generating the first or second boot refreshing pulses.

20. The buck-boost power converter of claim 19, wherein the switch control comprises circuitry to enable setting of at least one of the specified entry value, the specified exit value, and the specified successive quantity of times following manufacture of the switch control section.