Apparatus with main transistor-based switch and on-state linearization network

• US 10,116,298 B2
• Filed: 12/29/2016
• Issued: 10/30/2018
• Est. Priority Date: 03/31/2016
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Inventors: Scott, Baker, Maxim, George, Granger-Jones, Marcus, Leipold, Dirk Robert Walter, Choi, Jinsung
• Primary Examiner(s): Wells, Kenneth B
• Application Number:
  US15/393,699
• Publication Number:
  US 20170288659A1
• Time in Patent Office: 670 Days
• CPC Class Codes: H03K 17/145 in field-effect transistor switches
• CPC Class Codes: H03K 17/161 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit

Abstract

An apparatus including a main transistor-based switch having a first end node and a second end node and an ON-state linearization network that is coupled between the first end node and the second end node of the main transistor-based switch is disclosed. The ON-state linearization network is configured to receive a monitored signal that corresponds to a signal across the first end node and the second end node and cancel at least a portion of non-linear distortion generated by the main transistor-based switch when the main transistor-based switch is in an ON-state based on the monitored signal. A control signal applied to a control input of the ON-state linearization network causes the ON-state linearization network to activate when the main transistor-based switch is in the ON-state and to deactivate the ON-state linearization network when the main transistor-based switch is an OFF-state.

Claims

1. An apparatus comprising:

a main transistor-based switch having a first end node and a second end node comprising an N number of main field effect transistors (FETs) each having a first terminal, a second terminal, and a gate terminal and stacked in series such that the first terminal of a first main FET of the N number of main FETs is coupled to the first end node and the second terminal of an Nth main FET of the N number of main FETs is coupled to the second end node, wherein N is a finite number greater than one;

an ON-state linearization network that is coupled between the first end node and the second end node of the main transistor-based switch and configured to;

receive a monitored signal that corresponds to a signal across the first end node and the second end node;

cancel at least a portion of non-linear distortion generated by the main transistor-based switch when the main transistor-based switch is in an ON-state based on the monitored signal, wherein a control signal applied to a control input of the ON-state linearization network causes the ON-state linearization network to activate when the main transistor-based switch is in the ON-state and to deactivate the ON-state linearization network when the main transistor-based switch is an OFF-state; and

a first non-linear distortion cancellation (NDC) FET having a first NDC terminal coupled to the first terminal of the first main FET and a second NDC terminal coupled to the second terminal of the first main FET, and an NDC gate terminal coupled to both the control input and the second terminal of the Nth main FET; and

a control system having an output coupled to the control input and configured to provide the control signal.

2. The apparatus of claim 1 further including an OFF-state linearization network coupled between the gate terminal of the first main FET and the gate terminal of the Nth main FET.

3. The apparatus of claim 2 wherein the OFF-state linearization network comprises a K number of OFF-state noise cancelling (OSNC) FETs each having an input terminal, an output terminal, and a sense terminal, wherein individual ones of the K number of OSNC FETs have the input terminal coupled to the gate terminal of a nearest preceding one of the N number of main FETs, the output terminal coupled to the gate terminal of a nearest following one of the N number of main FETs and the sense terminal coupled to both the first terminal of the nearest following one of the N number of main FETs and the second terminal of the nearest preceding one of N number of main FETs.

4. The apparatus of claim 1 further including a resistor coupled between the control input and the NDC gate terminal of the first NDC FET.

5. The apparatus of claim 1 further including a shunt FET having a first shunt terminal coupled to the first end node of the main transistor-based switch, a second shunt terminal coupled to the NDC gate terminal of the first NDC FET, and a shunt gate terminal coupled to the gate terminal of the first main FET.

6. The apparatus of claim 5 further including a capacitor coupled between the NDC gate terminal of the first NDC FET and the second terminal of the Nth main FET.

7. The apparatus of claim 5 further including a second NDC FET having a third NDC terminal coupled to the first terminal of the Nth main FET and a fourth NDC terminal coupled to the second terminal of the Nth main FET, and a second NDC gate terminal coupled to the control input.

8. The apparatus of claim 7 further including a second capacitor coupled between the second NDC gate terminal of the first NDC FET and the first terminal of the first main FET of the N number of transistors.

9. The apparatus of claim 1 further including at least a second NDC FET having a third NDC terminal coupled to the second terminal of the first main FET and a fourth NDC terminal coupled to the second terminal of a second main FET of the N number of main FETs, and a second NDC gate terminal coupled to a second control input.

10. The apparatus of claim 9 including a second shunt FET having a third shunt terminal coupled to the second terminal of the first main FET, a fourth shunt terminal coupled to the second NDC gate terminal of the second NDC FET, and a second shunt gate terminal coupled to a gate terminal of a second FET of the N number of main FETs.

11. The apparatus of claim 10 wherein the control system has a second control output coupled to the second control input, wherein the control system is further configured to provide a second control signal that turns on the second NDC FET when the main transistor-based switch is in an ON-state and turns off the second NDC FET when the main transistor-based switch is in the OFF-state.

12. The apparatus of claim 10 further including a second capacitor coupled between the second NDC gate terminal of the second NDC FET and the second terminal of the Nth main FET.

13. The apparatus of claim 1 further including a first varactor configured FET having a first gate terminal coupled to the first terminal of the first main FET and a first drain terminal and a first source terminal coupled together with the NDC gate terminal.

14. The apparatus of claim 13 further including a second capacitor configured FET having a second gate terminal coupled to the second terminal of the first main FET and a second drain terminal and a second source terminal coupled together with the NDC gate terminal.

15. The apparatus of claim 1 further including an auxiliary (AUX) transistor-based switch having a first AUX node coupled to the NDC gate terminal and a second AUX node coupled to the second terminal of the Nth main FET.

16. The apparatus of claim 15 wherein the AUX transistor-based switch comprises an M number of AUX FETs each having a first AUX terminal, a second AUX terminal, and an AUX gate terminal and stacked in series and such that the first AUX terminal of a first FET of the M number of AUX FETs is coupled to the first AUX node and the second AUX terminal of an Mth one of the M number of AUX FETs is coupled to the second AUX node, wherein M is a finite number greater than one.

17. The apparatus of claim 16 wherein the control system is further configured to provide a control signal to each AUX gate terminal that turns on the AUX transistor-based switch when the main transistor-based switch is in an ON-state and turns off the AUX transistor-based switch when the main transistor-based switch is in the OFF-state.

18. The apparatus of claim 16 wherein the gate terminal of each of the N number of main FETs except for the first main FET is coupled to the AUX gate terminal of a corresponding one of the M number of AUX FETs.

19. The apparatus of claim 18 further including M−

2 number of shorting FETs that each has a first short terminal coupled to both the second terminal of a corresponding preceding one of the N number of main FETs and the first terminal of a corresponding following one of the N number of main FETs.

20. The apparatus of claim 19 wherein each of the M−

2 number of shorting FETs has a gate terminal coupled to the output of the control system and a second short terminal coupled to the second AUX terminal of a corresponding preceding one of the M number of AUX FETs and the first AUX terminal of a corresponding following one of the M number of AUX FETs.

21. The apparatus of claim 1 further including at least a second NDC FET having a second NDC gate terminal coupled to a second control input, a third NDC terminal coupled to the first NDC terminal, and a fourth NDC terminal.

22. The apparatus of claim 21 further including a detector that is configured to selectively couple the fourth NDC terminal to the second NDC terminal when the detector detects a predetermined condition.

23. The apparatus of claim 22 wherein the predetermined condition is a process corner.

24. The apparatus of claim 22 wherein the predetermined condition is a specified temperature range.