Cross-coupled, narrow pulse, high voltage level shifting circuit with voltage domain common mode rejection

• US 10,116,301 B2
• Filed: 07/12/2016
• Issued: 10/30/2018
• Est. Priority Date: 07/12/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Fesler, Robert, Aviral, Srivastava
• Primary Examiner(s): Hernandez, William
• Application Number:
  US15/208,297
• Publication Number:
  US 20180019749A1
• Time in Patent Office: 840 Days
• Field of Search: 326 82, 326 83, 326 88, 327108, 327109
• CPC Class Codes: H03K 17/165 by feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/018507 Interface arrangements
• CPC Class Codes: H03K 2217/0063 High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 2217/0072 Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 2217/0081 Power supply means, e.g. to the switch driver

Abstract

A system for high voltage level shifting includes a level shifting circuit having a high side circuit that receives a mixed signal having a common mode signal and a differential mode signal, and to attenuate the common mode signal in the mixed signal to generate an adjusted signal. The high side circuit generates a high output signal at a high output node in response to the adjusted signal. The system further includes a high side high voltage power transistor having a gate connected to the high output node of the high side circuit. The high side high voltage power transistor configured to provide a high portion of an output signal on a first output node in response to the high output signal.

Claims

1. A system, comprising:

a level shifting circuit including;

a high side circuit configured to receive a mixed signal having a common mode signal and a differential mode signal, and to attenuate the common mode signal in the mixed signal to generate an adjusted signal, wherein the high side circuit is further configured to generate a high output signal at a high output node in response to the adjusted signal;

a low side circuit configured to generate a differential signal in response to a high input signal and further configured to generate a low output signal at a low output node of the low side circuit in response to a low input signal; and

a high side high voltage power transistor having a gate connected to the high output node of the high side circuit, the high side high voltage power transistor configured to provide a high portion of an output signal on a first output node in response to the high output signal.

2. The system of claim 1, further comprising:

a low side high voltage power transistor having a gate connected to low output node of the low side circuit;

wherein the low side high voltage power transistor is configured to provide a low portion of the output signal on a second output node in response to the low output signal.

3. The system of claim 2, wherein the low side circuit is further configured to generate the differential signal on a first one of a set line and a reset line;

and

wherein the high side circuit comprises a cross coupled current mode cancellation circuit configured to attenuate the common mode signal of the mixed signal through cross coupled subtraction and according to a second signal on a second one of the set line and the reset line.

4. The system of claim 3, further comprising a current mirror configured to generate a mirrored signal by mirroring the mixed signal.

5. The system of claim 3, wherein the common mode signal is a slew signal associated with a change in voltage level of a supply voltage of the high side circuit, and wherein the second signal mirrors the slew signal.

6. A circuit, comprising:

a high side circuit, including;

current mirrors configured to generate mirrored currents that mirror a set signal and a reset signal that are generated in response to a set pulse and a reset pulse;

a cross coupled current mode cancellation circuit connected to the current mirrors, wherein the cross coupled current mode cancellation circuit is configured to attenuate at least a portion of a slew current from a first one of the mirrored currents to generate an adjusted first signal, and to generate a first voltage at a resistor according to the adjusted first signal; and

a high side driver configured to provide a high output signal according to activation to the first voltage.

7. The circuit of claim 6, further comprising a low side circuit, including a low side driver configured to receive a high input signal and to generate the set pulse and the reset pulse in response to the high input signal, wherein the high side circuit is isolated from the low side circuit;

wherein the high side circuit further includes a cross coupled detector circuit connected to the current mirrors and to the resistor of the cross coupled current mode cancellation circuit;

wherein the high side driver is configured to provide the high output signal according to activation of the high side driver; and

wherein the cross coupled detector circuit is configured to perform the activation of the high side driver according to the first voltage.

8. The circuit of claim 7, wherein the cross coupled detector circuit comprises N-channel devices, and wherein the slew current is associated with a change in voltage level of at least one supply voltage of the high side circuit.

9. The circuit of claim 6, wherein the first one of the mirrored currents mirrors a first one of the set signal and the reset signal;

and

wherein the cross coupled current mode cancellation circuit is further configured to attenuate the slew current in the first one of the mirrored currents according to a signal at a node complementary to a node carrying the first one of the mirrored currents.

10. The circuit of claim 6, wherein a current mirror of the current mirrors that mirrors the set signal mirrors the set signal with a different gain at different mirror transistors, and wherein the current mirror that mirrors the reset signal mirrors the reset signal with a different gain at different mirror transistors.

11. A gate driver circuit, comprising:

a first current mirror including;

a first reference current transistor having a source connected to a positive reference voltage port;

a first mirror transistor having a source connected to the positive reference voltage port and a gate connected to a gate and a drain of the first reference current transistor; and

a second mirror transistor having a source connected to the positive reference voltage port and a gate connected to the gate and the drain of the first reference current transistor;

a signaling set transistor connected in series between the drain of the first reference current transistor and a ground; and

a cross coupled current mode cancellation circuit including;

a first differential signal detection mirror transistor;

a first resistor connected in series with the drain of the second mirror transistor and a negative reference voltage port; and

a first common mode cancellation mirror transistor connected in parallel to the first resistor and in series between the drain of the second mirror transistor and the negative reference voltage port, and having a gate connected to a gate and a drain of a second differential signal detection mirror transistor.

12. The gate driver circuit of claim 11, further comprising:

a pulse generator, wherein the signaling set transistor has a gate connected to a first port of the pulse generator;

a high side driver having a first port connected to the positive reference voltage port; and

a cross coupled N-channel detector including a first cross coupled transistor and a second cross coupled transistor, wherein the first cross coupled transistor is connected in series between the first port of the high side driver and a gate of the second cross coupled transistor, and wherein the first cross coupled transistor has a gate connected to a drain of the second mirror transistor and the source of the second cross coupled transistor.

13. The gate driver circuit of claim 12, further comprising:

a second current mirror, including;

a second reference current transistor having a source connected to the positive reference voltage port;

a third mirror transistor having a source connected to the positive reference voltage port and a gate connected to a gate and a drain of the second reference current transistor; and

a fourth mirror transistor having a source connected to the positive reference voltage port and a gate connected to the gate and the drain of the second reference current transistor; and

a signaling reset transistor connected in series between the drain of the second reference current transistor and a ground, the signaling reset transistor having a gate connected to a second port of the pulse generator;

wherein the second differential signal detection mirror transistor is connected between the third mirror transistor and the negative reference voltage port.

14. The gate driver circuit of claim 13, further comprising:

a second resistor connected in series with a drain of the fourth mirror transistor and the negative reference voltage port;

wherein the first differential signal detection mirror transistor is connected in series between a drain of the first mirror transistor and the negative reference voltage port, and having a gate connected to the drain of the first mirror transistor and to a gate of a second common mode cancellation mirror transistor; and

wherein the second common mode cancellation mirror transistor is connected in parallel to the second resistor and in series between the drain of the fourth mirror transistor and the negative reference voltage port, and having a gate connected to a gate and a drain of the second differential signal detection mirror transistor.

15. The gate driver circuit of claim 14, wherein the second cross coupled transistor is connected in series between a second port of a high side driver and the gate of the first cross coupled transistor of the cross coupled N-channel detector;

and

wherein the second port of the high side driver is connected to the positive reference voltage port.

16. A method, comprising:

generating a set pulse in response to a received high input signal;

generating a set signal in response to the set pulse;

generating a first mirrored current that mirrors a current of the set signal;

generating a second mirrored current that mirrors a current at a first node that carries a reset signal when generated;

subtracting the second mirrored current from the first mirrored current to generate an adjusted first signal, the subtracting comprising attenuating a slew current in the first mirrored current to generate the adjusted first signal according to the second mirrored current;

generating a first voltage according to the adjusted first signal; and

activating a high side driver according to the first voltage and using a cross coupled detector circuit, the activating the high side driver causing the high side driver to provide a high output signal.

17. The method of claim 16, wherein the attenuating the slew current is performed using a cross coupled current mode cancellation circuit.

18. The method of claim 17, wherein the cross coupled detector circuit comprises one or more N-channel devices.

19. The method of claim 16, wherein the attenuating the slew current is performed in response to a change in voltage level of at least one reference voltage of a high side circuit in which the high side driver is disposed.