Inverse taper waveguides for low-loss mode converters

• US 10,120,135 B2
• Filed: 06/05/2017
• Issued: 11/06/2018
• Est. Priority Date: 04/30/2014
• Status: Active Grant

• Current Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Futurewei Technologies Incorporated (Huawei Investment & Holding Co., Ltd.)
• Inventors: Yang, Li, Pan, Huapu, Xu, Qianfan, Zheng, Dawei, Shen, Xiao
• Primary Examiner(s): Wong, Tina
• Application Number:
  US15/614,333
• Publication Number:
  US 20170269302A1
• Time in Patent Office: 519 Days
• Field of Search: None
• CPC Class Codes: G02B 6/1228 Tapered waveguides, e.g. integrated spot-size transformers for coupling with fibres G02B6/305
• CPC Class Codes: G02B 6/132 by deposition of thin films
• CPC Class Codes: G02B 6/136 by etching
• CPC Class Codes: G02B 6/14 Mode converters
• CPC Class Codes: G02B 6/305 and having an integrated mode-size expanding section, e.g. tapered waveguide

Abstract

An apparatus comprises a substrate comprising a silicon dioxide (SiO₂) material disposed on top of the substrate, a silicon waveguide comprising a first adiabatic tapering and enclosed in the silicon dioxide material, and a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering. A mode converter fabrication method comprises obtaining a mode converter comprising a substrate, a silicon waveguide disposed on the substrate and comprising a sidewall and a first adiabatic tapering, and a hard mask disposed on the silicon waveguide and comprising a silicon dioxide layer, wherein the hard mask does not cover the sidewall, and oxidizing the silicon waveguide and the hard mask, wherein oxidizing the silicon waveguide and the hard mask encloses the silicon waveguide within the silicon dioxide layer.

Claims

1. A mode converter fabrication method comprising:

obtaining a mode converter comprising;

a substrate,

a silicon waveguide disposed on the substrate and comprising a sidewall and a first adiabatic tapering, and

a hard mask disposed on the silicon waveguide and comprising a silicon dioxide (SiO₂) layer, wherein the hard mask does not cover the sidewall; and

oxidizing the silicon waveguide and the hard mask to enclose the silicon waveguide within the silicon dioxide layer.

2. The method of claim 1, wherein the substrate comprises a second silicon dioxide layer.

3. The method of claim 1, wherein the hard mask further comprises a silicon nitride (Si₃N₄) layer disposed on top of the silicon dioxide layer.

4. The method of claim 1, wherein oxidizing the silicon waveguide and the silicon dioxide layer comprises using dry thermal oxidation.

5. The method of claim 1, further comprising reducing a tip width of the silicon waveguide via the oxidizing.

6. The method of claim 1, further comprising patterning onto the substrate a second waveguide adjacent to the silicon waveguide.

7. The method of claim 6, wherein the second waveguide is in direct contact with the silicon dioxide layer.

8. The method of claim 6, wherein the second waveguide comprises a second adiabatic tapering.

9. The method of claim 8, wherein at least a first portion of the first adiabatic tapering and at least a second portion of the second adiabatic tapering abut each other.

10. The method of claim 8, wherein a first width of the first adiabatic tapering is widest at a first location along the substrate, and wherein a second width of the second adiabatic tapering is narrowest at the first location.

11. The method of claim 10, wherein the first width is narrowest at a second location along the substrate, and wherein the second width is widest at the second location.

12. The method of claim 11, wherein the first width is greater than 0.4 micrometers (μ

m) at the first location and is between about 50 nanometers (nm) and 60 nm at the second location, and wherein the second width is about 1 μ

m at the first location and is 15 μ

m or greater at the second location.

13. The method of claim 12, wherein a first thickness of the silicon waveguide is about 0.18 μ

m at the first location and about 0.15 μ

m at the second location, and wherein a second thickness of the silicon waveguide is between about 1 μ

m and about 15 μ

m at the first location and the second location.

14. The method of claim 1, further comprising further oxidizing the silicon waveguide and the hard mask to fully enclose the silicon waveguide within the silicon dioxide layer.

15. A mode converter fabrication method comprising:

fabricating onto a substrate a silicon waveguide that comprises a first adiabatic tapering and a sidewall, wherein a hard mask is disposed on the silicon waveguide and does not cover the sidewall, and wherein the hard mask comprises silicon dioxide (SiO₂) material;

fabricating a second waveguide onto the substrate, wherein the second waveguide comprises a second hard mask enclosing the second waveguide; and

oxidizing the silicon waveguide and the second waveguide until the silicon waveguide is enclosed within the silicon dioxide material.

16. The method of claim 15, further comprising reducing a tip width of the silicon waveguide via the oxidizing.

17. The method of claim 15, wherein the second waveguide comprises a second adiabatic tapering.

18. The method of claim 17, wherein at least a first portion of the first adiabatic tapering and at least a second portion of the second adiabatic tapering abut each other.

19. The method of claim 17, wherein a first width of the first adiabatic tapering is widest at a first location along the substrate and narrowest at a second location along the substrate, wherein a second width of the second adiabatic tapering is narrowest at the first location and widest at the second location.

20. The method of claim 15, wherein the silicon waveguide is separated from the second waveguide by a low-index material, and wherein the substrate comprises a silicon (Si) layer and a buried oxide (BOX) layer.