Method and apparatus for dense hyper IO digital retention
First Claim
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1. A specialized computer architecture computing system comprising:
- a computer processor in electronic communication with an internal system bus on a motherboard of the specialized computer architecture computing system;
a random access memory storage in electronic communication with the computer processor through the internal system bus on the motherboard of the specialized computer architecture computing system;
the computer processor configured to access through the internal system bus data stored in the random access memory storage;
the computer processor configured to process all data by generating unencoded raw data blocks by concatenating together a plurality of unique unencoded data stored in the random access memory storage, andthe computer processor configured to perform operations on the generated unencoded raw data blocks,wherein the computer processor utilizes bit markers to access some of the unique unencoded data stored in the random access memory storage.
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Abstract
System and method to encode and decode raw data. The method to encode includes receiving a block of uncoded data, decomposing the block of uncoded data into a plurality of data vectors, mapping each of the plurality of data vectors to a bit marker; and storing the bit marker in a memory to produce an encoded representation of the uncoded data. Encoding may further include decomposing the block of uncoded data into default data and non-default data, and mapping only the non-default data. In some embodiments, bit markers may include a seed value and replication rule, or a fractalized pattern.
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Citations
36 Claims
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1. A specialized computer architecture computing system comprising:
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a computer processor in electronic communication with an internal system bus on a motherboard of the specialized computer architecture computing system; a random access memory storage in electronic communication with the computer processor through the internal system bus on the motherboard of the specialized computer architecture computing system; the computer processor configured to access through the internal system bus data stored in the random access memory storage; the computer processor configured to process all data by generating unencoded raw data blocks by concatenating together a plurality of unique unencoded data stored in the random access memory storage, and the computer processor configured to perform operations on the generated unencoded raw data blocks, wherein the computer processor utilizes bit markers to access some of the unique unencoded data stored in the random access memory storage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A specialized computer architecture computing system comprising:
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a computer processor in electronic communication with an internal system bus on a motherboard of the specialized computer architecture computing system; a random access memory storage in electronic communication with the computer processor through the internal system bus on the motherboard of the specialized computer architecture computing system; the computer processor configured to access through the internal system bus data stored in the random access memory storage; the computer processor configured to process all data by generating unencoded raw data blocks by concatenating together a plurality of unique unencoded data stored in the random access memory storage, and the computer processor configured to perform operations on the generated unencoded raw data blocks, wherein the computer processor is configured to process a first computer data file and a second computer data file, the first and second computer data files generated by the computer processor by concatenating together a plurality of unique data stored in the random access storage, wherein the first and second computer data files each comprise at least one common unique data retrieved from the random storage. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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Specification