Software-assisted wireless coordination of audio playback

• US 10,120,641 B2
• Filed: 08/15/2017
• Issued: 11/06/2018
• Est. Priority Date: 12/13/2016
• Status: Active Grant

• Current Assignee: B&W Group Ltd. (Masimo Corporation)
• Original Assignee: EVA Automation, Inc.
• Inventors: Lay, Leo, Chadd, Adrian Harold, Wang, Haisong, Zhao, Shiwei, Li, Li, Yu, Gaylord
• Primary Examiner(s): Saunders, Jr., Joseph
• Application Number:
  US15/678,083
• Publication Number:
  US 20180167646A1
• Time in Patent Office: 448 Days
• CPC Class Codes: G06F 3/165 Management of the audio stream, e.g. setting of volume, audio stream path
• CPC Class Codes: H04H 60/80 characterised by transmission among terminal devices
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04J 3/0661 using timestamps
• CPC Class Codes: H04L 65/60 Network streaming of media packets
• CPC Class Codes: H04L 65/61 for supporting one-way streaming services, e.g. Internet radio
• CPC Class Codes: H04L 65/65 Network streaming protocols, e.g. real-time transport protocol [RTP] or real-time control protocol [RTCP]
• CPC Class Codes: H04L 65/80 Responding to QoS
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0016 correction of synchronization errors
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04M 1/72442 for playing music files
• CPC Class Codes: H04N 21/233 Processing of audio elementary streams monitoring, identification or recognition of audio in broadcast systems H04H60/58
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/8113 comprising music, e.g. song in MP3 format
• CPC Class Codes: H04R 2227/005 Audio distribution systems for home, i.e. multi-room use
• CPC Class Codes: H04R 2420/07 Applications of wireless loudspeakers or wireless microphones
• CPC Class Codes: H04R 27/00 Public address systems circuits for preventing acoustic reaction H04R3/02; circuits for distributing signals to loudspeakers H04R3/12; monitoring or testing arrangements for public address systems H04R29/007; amplifiers H03F
• CPC Class Codes: H04R 3/12 for distributing signals to two or more loudspeakers specially adapted for hearing aids H04R25/407
• CPC Class Codes: H04W 56/0015 : one node acting as a reference for the others
• CPC Class Codes: H04W 56/005 : compensating for timing error by adjustment in the receiver

Abstract

A processor in an electronic device maintains coordination between a system clock provided by a system clock circuit and an interface clock provided by a clock circuit. Then, the processor may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between the interface clock and a second interface clock in the second electronic device. Moreover, the processor adjusts, based on the relative drift, the system clock circuit to eliminate the relative drift. Next, the processor may determine a remaining time offset between the interface clock and the second interface clock. Furthermore, the processor modifies a future time when the electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and may perform the playback operation at the corrected future time.

Claims

1. An electronic device, comprising:

a system clock circuit configured to provide a system clock in the electronic device;

a processor, coupled to the system clock, configured to execute software;

one or more antennas;

an interface clock circuit that is configured to provide an interface clock; and

an interface circuit communicatively coupled to the one or more antennas, the interface clock circuit and the processor, wherein the interface circuit is configured to;

receive, from the one or more antennas, packets associated with a second electronic device, wherein a given packet includes a transmit time, based on a second interface clock in the second electronic device when the second electronic device transmitted the given packet;

store receive times when the packets were received, wherein the receive times are based on the interface clock; and

receive, from the one or more antennas, information associated with the second electronic device specifying a future time when the electronic device is to perform a playback operation; and

wherein the processor is configured to;

maintain coordination between the system clock and the interface clock, wherein the interface clock has a higher frequency than the system clock;

calculate, based on differences between the transmit times and the receive times, relative drift as a function of time between the interface clock and the second interface clock;

adjust, based on the relative drift, the system clock circuit to eliminate the relative drift, wherein the relative drift, which is based on the interface clock, provides higher resolution than the system clock;

determine a remaining time offset between the interface clock and the second interface clock;

modify the future time based on the remaining time offset to determine a corrected future time; and

perform the playback operation at the corrected future time.

2. The electronic device of claim 1, wherein, prior to performing the playback operation, the processor is further configured to:

disable interrupts in the electronic device; and

occupy at least a portion of a software stack by executing a loop to reduce a latency associated with performing the playback operation.

3. The electronic device of claim 1, further comprising memory, coupled to the processor, configured to store a program module, wherein, when executed by the processor, the program module causes the electronic device to perform the maintaining, the calculating, the adjusting, the determining, the modifying and the performing.

4. The electronic device of claim 1, wherein the transmit time is included in the given packet in one of:

a payload; and

a media access control (MAC) header.

5. The electronic device of claim 1, wherein the transmit time and the receive time are stored on opposite ends of a payload of the given packet;

and

wherein the processor is configured to determine a duration of the payload and to add the duration to the remaining offset time.

6. The electronic device of claim 1, wherein the packets include audio data in payloads;

wherein the electronic device is configured to store the audio data in a queue; and

wherein the playback operation involves outputting the audio data from the queue.

7. The electronic device of claim 1, wherein the adjusting of the system clock and the modifying of the future time coordinate the playback operation in a clock domain of the interface clock to within a predefined value of a clock domain of the second interface clock.

8. The electronic device of claim 1, wherein the packets include control packets.

9. The electronic device of claim 1, wherein the second electronic device is a master and the electronic device is a slave.

10. The electronic device of claim 1, wherein the receive times are associated with a wireless ranging capability of the interface circuit.

11. The electronic device of claim 1, wherein, when a reset of the interface circuit or a second interface circuit in the second electronic device occurs, the processor is configured to mirror the interface clock by sampling and holding a counter value in a counter in the interface circuit that corresponds to the interface clock prior to the counter being reset;

and

wherein the mirrored counter value allows the interface circuit to reduce the relative drift while the interface circuit restores frequency lock with the second interface clock based on additional packets with additional transmit times, which are associated with the second electronic device, and which are received by the interface circuit.

12. A non-transitory computer-readable storage medium for use with an electronic device, the computer-readable storage medium storing a program module that, when executed by the electronic device, coordinates a playback operation by causing the electronic device to perform one or more operations comprising:

maintaining coordination between a system clock provided by a system clock circuit in the electronic device and an interface clock provided by an interface clock circuit in the electronic device, wherein the interface clock has a higher frequency than the system clock;

calculating, based on differences between receive times when an interface circuit in the electronic device received packets associated with a second electronic device and transmit times, included in the packets, when the second electronic device transmitted the packets, relative drift as a function of time between the interface clock and a second interface clock in the second electronic device, wherein a given packet includes a transmit time, based on the second interface clock, when the second electronic device transmitted the given packet;

adjusting, based on the relative drift, the system clock circuit to eliminate the relative drift, wherein the relative drift, which is based on the interface clock, provides higher resolution than the system clock;

determining a remaining time offset between the interface clock and the second interface clock;

modifying, based on the remaining time offset, a future time, which was received from the interface circuit, when the electronic device is to perform the playback operation to determine a corrected future time; and

performing the playback operation at the corrected future time.

13. The computer-program product of claim 12, wherein the one or more operations comprise:

disabling interrupts in the electronic device; and

occupying at least a portion of a software stack by executing a loop to reduce a latency associated with performing the playback operation.

14. The computer-program product of claim 12, wherein the transmit time is included in the given packet in one of:

a payload; and

a media access control (MAC) header.

15. The computer-program product of claim 12, wherein the transmit time and the receive time are stored on opposite ends of a payload of the given packet;

and

wherein the one or more operations comprise;

determining a duration of the payload; and

adding the duration to the remaining offset time.

16. The computer-program product of claim 12, wherein the packets include audio data in payloads;

wherein the one or more operations comprise storing the audio data in a queue; and

wherein the performing the playback operation involves outputting the audio data from the queue.

17. The computer-program product of claim 12, wherein the adjusting of the system clock and the modifying of the future time coordinate the playback operation in a clock domain of the interface clock to within a predefined value of a clock domain of the second interface clock.

18. A method for coordinating a playback operation, comprising:

by a processor in an electronic device;

maintaining coordination between a system clock provided by a system clock circuit in the electronic device and an interface clock provided by an interface clock circuit in the electronic device, wherein the interface clock has a higher frequency than the system clock;

calculating, based on differences between receive times when an interface circuit in the electronic device received packets associated with the second electronic device and transmit times, included in the packets, when the second electronic device transmitted the packets, relative drift as a function of time between the interface clock and a second interface clock in the second electronic device, wherein a given packet includes a transmit time, based on the second interface clock, when the second electronic device transmitted the given packet;

adjusting, based on the relative drift, the system clock circuit to eliminate the relative drift, wherein the relative drift, which is based on the interface clock, provides higher resolution than the system clock;

determining a remaining time offset between the interface clock and the second interface clock;

modifying, based on the remaining time offset, a future time, which was received from the interface circuit, when the electronic device is to perform the playback operation to determine a corrected future time; and

performing the playback operation at the corrected future time.

19. The method of claim 18, wherein, prior to performing the playback operation, the method further comprises:

disabling interrupts in the electronic device; and

occupying at least a portion of a software stack by executing a loop to reduce a latency associated with performing the playback operation.

20. The method of claim 18, wherein the transmit time is included in the given packet in one of:

a payload; and

a media access control (MAC) header.

21. The method of claim 18, wherein the transmit time and the receive time are stored on opposite ends of a payload of the given packet;

and

wherein the method further comprises determining a duration of the payload and adding the duration to the remaining offset time.

22. The method of claim 18, wherein the packets include audio data in payloads;

wherein the method further comprises storing the audio data in a queue; and

wherein the performing of the playback operation involves outputting the audio data from the queue.