Power supply controller system and semiconductor device

• US 10,120,742 B2
• Filed: 04/28/2017
• Issued: 11/06/2018
• Est. Priority Date: 05/27/2016
• Status: Active Grant

• Current Assignee: Omron Corporation
• Original Assignee: Omron Corporation
• Inventors: Ueda, Takamasa, Muneta, Yasuo
• Primary Examiner(s): Butler, Sarai E
• Application Number:
  US15/499,905
• Publication Number:
  US 20170344418A1
• Time in Patent Office: 557 Days
• Field of Search: 714 22, 714 24
• CPC Class Codes: G05B 2219/24125 Watchdog, check at timed intervals
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 9/442 Shutdown

Abstract

A power supply controller system includes a power supply portion, arithmetic processing portions, and first and second monitoring circuits configured to monitor an integrity of power supply of the power supply portion. The first monitoring circuit instructs a second arithmetic processing portion to stop an operation thereof when a first watchdog timer is not reset for a predetermined period of time. The second monitoring circuit instructs a first arithmetic processing portion to stop an operation thereof when a second watchdog timer is not reset for a predetermined period of time. The first monitoring circuit further includes a third watchdog timer periodically reset by any one of the first arithmetic processing portion and the second arithmetic processing portion and instructs another arithmetic processing portion to stop an operation thereof when the third watchdog timer is not reset for a predetermined period of time.

Claims

1. A power supply controller system comprising:

a power supply portion;

a first arithmetic processing portion and a second arithmetic processing portion configured to receive power from the power supply portion and operate; and

a first monitoring circuit and a second monitoring circuit configured to monitor an integrity of power supply of the power supply portion,

wherein the first monitoring circuit includes a first watchdog timer periodically reset by the first arithmetic processing portion and instructs the second arithmetic processing portion to stop an operation thereof when the first watchdog timer is not reset for a first predetermined period of time,

the second monitoring circuit includes a second watchdog timer periodically reset by the second arithmetic processing portion and instructs the first arithmetic processing portion to stop an operation thereof when the second watchdog timer is not reset for a second predetermined period of time, and

the first monitoring circuit further includes a third watchdog timer periodically reset by any one of the first arithmetic processing portion and the second arithmetic processing portion and instructs another arithmetic processing portion to stop an operation thereof when the third watchdog timer is not reset for a third predetermined period of time.

2. The power supply controller system according to claim 1, wherein the first monitoring circuit includes a first power supply monitoring portion configured to monitor an integrity of the power supply portion configured to supply power to the first arithmetic processing portion and the second arithmetic processing portion and instructs the first arithmetic processing portion and the second arithmetic processing portion to stop operations thereof if the first power supply monitoring portion detects that an abnormality occurs in the power supply portion, and

the second monitoring circuit includes a second power supply monitoring portion configured to monitor an integrity of the power supply portion configured to supply power to the first arithmetic processing portion and the second arithmetic processing portion and instructs the first arithmetic processing portion and the second arithmetic processing portion to stop operations thereof if the second power supply monitoring portion detects that an abnormality occurs in the power supply portion.

3. The power supply controller system according to claim 2, wherein the first power supply monitoring portion and the second power supply monitoring portion are constituted of semiconductor devices manufactured by different processes.

4. The power supply controller system according to claim 1, wherein watchdog timers are not mounted in the first arithmetic processing portion and the second arithmetic processing portion.

5. A semiconductor device which monitors an integrity of power supply of a power supply portion and an integrity of a first arithmetic processing portion and a second arithmetic processing portion in a power supply controller system including the first arithmetic processing portion and the second arithmetic processing portion receiving power from the power supply portion and operating, the semiconductor device comprising:

a first watchdog timer periodically reset by the first arithmetic processing portion;

a second watchdog timer periodically reset by the second arithmetic processing portion;

a power supply monitoring portion configured to monitor an integrity of the power supply portion; and

a controller,

wherein the controller instructs the second arithmetic processing portion to stop an operation thereof when the first watchdog timer is not reset for a first predetermined period of time,

instructs the first arithmetic processing portion to stop an operation thereof when the second watchdog timer is not reset for a second predetermined period of time, and

instructs the first arithmetic processing portion and the second arithmetic processing portion to stop operations thereof if the power supply monitoring portion detects that an abnormality occurs in the power supply portion.