Techniques to recover data using exclusive OR (XOR) parity information

• US 10,120,751 B2
• Filed: 09/25/2015
• Issued: 11/06/2018
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Khan, Jawad B., Ramalingam, Anand S., Kalavade, Pranav
• Primary Examiner(s): Knapp, Justin R
• Application Number:
  US14/866,291
• Publication Number:
  US 20170091022A1
• Time in Patent Office: 1,138 Days
• Field of Search: None
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

Examples may include techniques to recover data from a solid state drive (SSD) using exclusive OR (XOR) parity information. Data saved to non-volatile types of block-erasable memory such as NAND memory included in the SSD may be recovered via use of XOR parity information saved to types of write-in-place memory such as a 3-dimensional cross-point memory also included in the SSD.

Claims

1. An apparatus comprising:

a plurality of block-erasable memory devices having at least a first and a second memory page;

a write-in-place memory device; and

an exclusive OR (XOR) engine, at least a portion of the XOR engine in hardware, the XOR engine to generate XOR parity information based on data stored to the first and the second memory pages of a first number of planes spanning across more than one block-erasable memory device from among the plurality of block-erasable memory devices, the data stored to the first and second memory pages comprising at least first and second XOR stripes and cause the XOR parity information for the first and second XOR stripes to be XORed together to a same physical memory address of the write-in-place memory device based on a data structure that indicates a mapping of the XOR parity information to one or more physical memory addresses.

2. The apparatus of claim 1, the plurality of block erasable memory devices comprising a plurality of NAND memory dies and the write in place memory device comprising a 3-D cross-point memory die.

3. The apparatus of claim 2, individual NAND memory dies of the plurality of NAND memory dies including multiple NAND planes, the XOR parity information generated by the XOR engine based on a first number of NAND planes of more than one individual NAND memory die having data stored to the first memory pages for the first number of NAND planes XORed together and having data stored to the second memory pages for the first number of NAND planes XORed together, the data stored to the first and second memory pages comprising respective first and second XOR stripes.

4. The apparatus of claim 3, comprising:

a storage controller, at least a portion of the storage controller in hardware, the storage controller to;

determine one or more physical memory addresses in the 3-D cross-point memory die to store XOR parity information generated by the XOR engine for the first and second XOR stripes; and

cause the XOR parity information to be stored to the one or more physical memory addresses.

5. The apparatus of claim 4, the storage controller to determine the one or more physical memory addresses based on a data structure that indicates a mapping of the XOR parity information generated by the XOR engine for storing XOR parity information to the one or more physical memory addresses in the 3-D cross-point memory die.

6. The apparatus of claim 5, the mapping to indicate storing the XOR parity information for third and fourth XOR stripes XORed together to a separate physical memory address in order to increase a protection level to recover data stored to the plurality of NAND memory dies.

7. The apparatus of claim 6, the data structure to comprise a lookup table capable of being saved to the write-in-place memory device responsive to a power fail event via a power loss imminent (PLI) mechanism.

8. The apparatus of claim 5, the storage controller to cause the data structure that indicates the mapping of the XOR parity information to be stored in the 3-D cross-point memory die.

9. The apparatus of claim 1, comprising a transfer buffer including volatile memory to at least temporarily store the XOR parity information generated by the XOR engine prior to the XOR parity information being stored to the write-in-place memory device.

10. A method implemented at a storage device comprising:

storing data to a plurality of block-erasable memory devices that individually include multiple memory planes, each memory plane including at least first and second memory pages to store the data;

generating exclusive OR (XOR) parity information based on data stored to first and second memory pages of a first number of planes spanning across more than one block-erasable memory device from among the plurality of block-erasable memory devices, the data stored to the first and second memory pages comprising first and second XOR stripes; and

storing the XOR parity information for the first and second XOR stripes at one or more physical memory addresses of a write-in-place memory device based on a data structure that indicates a mapping of the XOR parity information to the one or more physical memory addresses, the mapping to indicate storing the XOR parity information for the first and second XOR stripes XORed together to a same physical memory address in order to decrease an amount of write-in-place memory of the write-in-place memory device used to store XOR parity information for the first and second XOR stripes that are XORed together.

11. The method of claim 10, the plurality of block erasable memory devices comprising a plurality of NAND memory dies and the write in place memory device comprising a 3-D cross-point memory die.

12. The method of claim 10, comprising:

recovering data stored to the first or second memory pages using the XOR parity information stored to the write-in-place memory device, the data recovered responsive to an uncorrectable error to a portion of the data stored to the first or second memory pages.

13. The method of claim 10, comprising:

causing the data structure that indicates the mapping of the XOR parity information to be stored to the write-in-place memory device.

14. The method of claim 13, the data structure comprising a lookup table capable of being saved to the write-in-place memory device responsive to a power fail event using a power loss imminent (PLI) mechanism.

15. The method of claim 11, comprising:

storing, at least temporarily, the XOR parity information at a transfer buffer including volatile memory prior to storing the XOR parity information to the 3-D cross-point memory device.

16. A system comprising:

a processor for a computing platform;

a storage device coupled with the computing platform, the storage device including;

a storage controller, at least a portion of the storage controller in hardware;

a plurality of block-erasable memory devices having first and second memory pages;

a write-in-place memory device; and

an exclusive OR (XOR) engine, at least a portion of the XOR engine in hardware, the XOR engine to generate XOR parity information based on data stored to the first and the second memory pages of a first number of planes spanning across more than one block-erasable memory device from among the plurality of block-erasable memory devices, the data stored to the first and second memory pages, the XOR parity information comprising at least first and second XOR stripes and cause the XOR parity information for the first and second XOR stripes to be XORed together to a same physical memory address of the write-in-place memory device based on a data structure that indicates a mapping of the XOR parity information to one or more physical memory addresses.

17. The system of claim 16, the plurality of block erasable memory devices comprising a plurality of NAND memory dies and the write in place memory device comprising a 3-D cross-point memory die.

18. The system of claim 17, individual NAND memory dies of the plurality of NAND memory dies including multiple NAND planes, the XOR parity information generated by the XOR engine based on a first number of NAND planes of more than one individual NAND memory die having data stored to the first memory pages for the first number of NAND planes XORed together and having data stored to the second memory pages for the first number of NAND planes XORed together, the data stored to the first and second memory pages comprising respective first and second XOR stripes.

19. The system of claim 18, comprising the storage controller to:

determine one or more physical memory addresses in the 3-D cross-point memory die to store XOR parity information generated by the XOR engine for the first and second XOR stripes; and

cause the XOR parity information to be stored to the one or more physical memory addresses.

20. The system of claim 19, the storage controller to determine the one or more physical memory addresses based on a data structure that indicates a mapping of the XOR parity information generated by the XOR engine for storing XOR parity information to the one or more physical memory addresses in the 3-D cross-point memory die, the mapping to indicate storing the XOR parity information for the first and second XOR stripes XORed together to separate physical memory addresses in order to increase a protection level to recover data stored to the plurality of NAND memory dies.

21. The system of claim 20, the storage controller to cause the data structure that indicates the mapping of the XOR parity information to be stored in the write-in-place memory device.

22. The system of claim 17 comprising a transfer buffer including volatile memory to at least temporarily store the XOR parity information generated by the XOR engine prior to the XOR parity information being stored to the 3-D cross-point memory die.

23. The system of claim 16, comprising a digital display coupled with the processor to present a user interface view.