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Apparatus and method for lazy translation lookaside buffer (TLB) coherence

  • US 10,120,814 B2
  • Filed: 04/01/2016
  • Issued: 11/06/2018
  • Est. Priority Date: 04/01/2016
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • one or more cores to execute instructions and process data;

    one or more translation lookaside buffers (TLBs) each comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions;

    one or more epoch counters each programmed with a specified epoch value, wherein the epoch value is selected to be less than the time between occurrences of context switches on the processor; and

    TLB validation logic to validate a specified set of TLB entries at intervals specified by the epoch value wherein the epoch value is set between 1 and 100 microseconds.

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