Apparatus and method for lazy translation lookaside buffer (TLB) coherence

• US 10,120,814 B2
• Filed: 04/01/2016
• Issued: 11/06/2018
• Est. Priority Date: 04/01/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Doshi, Kshitij A., Hughes, Christopher J.
• Primary Examiner(s): Giardino, Jr., Mark A
• Application Number:
  US15/089,211
• Publication Number:
  US 20170286316A1
• Time in Patent Office: 949 Days
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency

Abstract

An apparatus and method are described for managing TLB coherence. For example, one embodiment of a processor comprises: one or more cores to execute instructions and process data; one or more translation lookaside buffers (TLBs) each comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions; one or more epoch counters each programmed with a specified epoch value; and TLB validation logic to validate a specified set of TLB entries at intervals specified by the epoch value.

Claims

1. A processor comprising:

one or more cores to execute instructions and process data;

one or more translation lookaside buffers (TLBs) each comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions;

one or more epoch counters each programmed with a specified epoch value, wherein the epoch value is selected to be less than the time between occurrences of context switches on the processor; and

TLB validation logic to validate a specified set of TLB entries at intervals specified by the epoch value wherein the epoch value is set between 1 and 100 microseconds.

2. The processor as in claim 1 wherein the epoch counter of a first core is advanced in accordance with the epoch value and wherein the TLB validation logic of the first core responsively sets a revalidate bit in each of the specified set of TLB entries indicating that each TLB entry in the specified set must be re-validated before being used safely.

3. The processor as in claim 2 wherein each of the revalidate bits are to be stored in a separate array managed by software or to be stored within individual page table entries (PTEs).

4. The processor as in claim 2 wherein the first core accesses a first TLB associated with and/or integral to the first core when requesting address translations, the first core to determine a TLB hit resulting from a translation being located in the TLB or a TLB miss if the translation is not located in the TLB.

5. The processor as in claim 4 wherein in response to a TLB lookup, a translation associated with the TLB entry resulting in the TLB lookup is provided if the revalidate bit associated with the TLB entry is not set.

6. The processor as in claim 5 wherein if the revalidate bit associated with the TLB entry is set, then the TLB entry is to be flushed and a TLB miss indication provided to the MMU responsive to the TLB lookup.

7. A method comprising:

executing instructions on a set of one or more cores to execute instructions and process data;

caching virtual-to-physical address translations usable by the set of one or more cores within one or more translation lookaside buffers (TLBs) when executing the instructions;

programming one or more epoch counters with specified epoch values, wherein the epoch value is selected to be less than a rate at which context switches are to occur on the processor; and

validating a specified set of TLB entries at intervals specified by one or more of the epoch values wherein the epoch value is set between 1 and 100 microseconds.

8. The method as in claim 7 wherein the epoch counter of a first core is advanced in accordance with an epoch value, the method further comprising setting a revalidate bit in each of the specified set of TLB entries indicating that each TLB entry in the specified set must be re-validated before being used safely.

9. The method as in claim 8 wherein each of the revalidate bits are to be stored in a separate array managed by software or to be stored within individual page table entries (PTEs).

10. The method as in claim 8 further comprising:

determining a TLB hit resulting from a translation being located in one of the TLBs or a TLB miss if the translation is not located in the TLB.

11. The method as in claim 10 wherein in response to a TLB lookup, a translation associated with the TLB entry resulting in the TLB lookup is provided if the revalidate bit associated with the TLB entry is not set.

12. The method as in claim 11 wherein if the revalidate bit associated with the TLB entry is set, then the TLB entry is to be flushed and a TLB miss indication provided responsive to the TLB lookup.

13. A system comprising:

a memory to store instructions and data;

a processor to execute the instructions and process the data;

a graphics processor to perform graphics operations in response to graphics instructions;

a network interface to receive and transmit data over a network;

an interface for receiving user input from a mouse or cursor control device, the plurality of cores executing the instructions and processing the data responsive to the user input;

the processor comprising;

one or more cores to execute instructions and process data;

one or more translation lookaside buffers (TLBs) each comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions;

one or more epoch counters each programmed with a specified epoch value, wherein the epoch value is selected to be less than the time between occurrences of context switches on the processor; and

TLB validation logic to validate a specified set of TLB entries at intervals specified by the epoch value, wherein the epoch value is set between 1 and 100 microseconds.

14. The system as in claim 13 wherein epoch counter of a first core is advanced in accordance with the epoch value and wherein the TLB validation logic of the first core responsively sets a revalidate bit in each of the specified set of TLB entries indicating that each TLB entry in the specified set must be re-validated before being used safely.

15. The system as in claim 14 wherein each of the revalidate bits are to be stored in a separate array managed by software or to be stored within individual page table entries (PTEs).

16. The system as in claim 14 wherein the first core accesses a first TLB associated with and/or integral to the first core when requesting address translations, the first core to determine a TLB hit resulting from a translation being located in the TLB or a TLB miss if the translation is not located in the TLB.

17. The system as in claim 16 wherein in response to a TLB lookup, a translation associated with the TLB entry resulting in the TLB lookup is provided if the revalidate bit associated with the TLB entry is not set.

18. The system as in claim 17 wherein if the revalidate bit associated with the TLB entry is set, then the TLB entry is to be flushed and a TLB miss indication provided to the MMU responsive to the TLB lookup.