Integrated fan-out package and layout method thereof

• US 10,120,971 B2
• Filed: 08/30/2016
• Issued: 11/06/2018
• Est. Priority Date: 08/30/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lo, Wan-Yu, Liu, Chin-Chou, Yang, Kuo-Nan, Chang, Yu-Jen
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US15/250,934
• Publication Number:
  US 20180060479A1
• Time in Patent Office: 798 Days
• Field of Search: 257773, 257786
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/1411 the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/14515 Bump connectors having different functions
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81192 : wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

An integrated fan-out package and a layout method thereof are provided. One integrated fan-out package includes a die and a fan-out substrate. The die has an interconnect structure therein. The fan-out substrate has a redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof. The first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a redistribution layer of the redistribution layer structure, and an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.

Claims

1. An integrated fan-out package, comprising:

a die having an interconnect structure therein; and

a fan-out substrate having a conductive redistribution layer structure therein and a plurality of first conductive bumps on a first surface thereof,

wherein the first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a conductive redistribution layer of the conductive redistribution layer structure,

wherein the fan-out substrate further has a plurality of second conductive bumps on the first surface thereof and aside the first conductive bumps, and the second conductive bumps are not in physical contact with the interconnect layer but in physical contact with the conductive redistribution layer, and

wherein the first and second conductive bumps are overlapped with each of the fan-out substrate and the die, and an underfill layer encapsulates the first and second conductive bumps.

2. The integrated fan-out package of claim 1, wherein an aspect ratio of the first conductive bumps ranges from about 1/5 to 1/8.

3. The integrated fan-out package of claim 1, wherein a width of the first conductive bumps is about 5 μ

m to 10 μ

m.

4. The integrated fan-out package of claim 1, further comprising a dielectric layer encapsulating the first conductive bumps, wherein a dielectric constant of the dielectric layer is equal to or less than about 3.

5. The integrated fan-out package of claim 1, wherein the interconnect layer comprises a plurality of first conductive lines, the conductive redistribution layer comprises a plurality of second conductive lines, and an area of a total of overlapped regions of the first and second conductive lines is less than a preset value determined by an integrated fan-out package performance according to capacitance and inductance information or a coupling effect between the die and the fan-out substrate.

6. The integrated fan-out package of claim 1, wherein the interconnect layer comprises a plurality of first conductive lines, the conductive redistribution layer comprises a plurality of second conductive lines, and the first conductive lines are non-parallel to the second conductive lines.

7. The integrated fan-out package of claim 1, wherein an aspect ratio of the second conductive bumps is the same as an aspect ratio of the first conductive bumps.

8. The integrated fan-out package of claim 1, wherein an aspect ratio of the second conductive bumps is different from an aspect ratio of the first conductive bumps.

9. The integrated fan-out package of claim 1, wherein an aspect ratio of the first conductive bumps ranges from about 1/3 to 1/10.

10. An integrated fan-out package, comprising:

a die having an interconnect structure therein; and

a fan-out substrate having a conductive redistribution layer structure therein and a plurality of first conductive bumps and a plurality of second conductive bumps on a first surface thereof,

wherein the first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a conductive redistribution layer of the conductive redistribution layer structure, and the second conductive bumps are not in physical contact with the interconnect layer but in physical contact with the conductive redistribution layer, and

wherein the interconnect layer of the interconnect structure comprises a plurality of first conductive lines, the conductive redistribution layer of the conductive redistribution layer structure comprises a plurality of second conductive lines, the first conductive lines of the die are, in a top view, non-parallel to the second conductive lines of the fan-out substrate, and in the top view, an area of a total of regions where the first conductive lines of the interconnect layer of the die are overlapped with the second conductive lines of the conductive redistribution layer of the fan-out substrate is smaller than a preset value determined by an integrated fan-out package performance according to capacitance and inductance information or a coupling effect between the die and the fan-out substrate, wherein the plurality of first conductive bumps and the plurality of second conductive bumps are overlapped with each of the fan-out substrate and the die.

11. The integrated fan-out package of claim 10, further comprising a dielectric layer encapsulating the first conductive bumps, wherein a dielectric constant of the dielectric layer is equal to or less than about 3.

12. The integrated fan-out package of claim 10, wherein an aspect ratio of the second conductive bumps is the same as the aspect ratio of the first conductive bumps.

13. The integrated fan-out package of claim 10, wherein an aspect ratio of the second conductive bumps is different from the aspect ratio of the first conductive bumps.

14. An integrated fan-out package, comprising:

a die having an interconnect structure therein; and

a fan-out substrate having a conductive redistribution layer structure therein and a plurality of first conductive bumps and a plurality of second conductive bumps on a first surface thereof,

wherein the first conductive bumps are in physical contact with an interconnect layer of the interconnect structure and a conductive redistribution layer of the conductive redistribution layer structure, and the second conductive bumps are not in physical contact with the interconnect layer but in physical contact with the conductive redistribution layer, and

wherein the interconnect layer of the interconnect structure comprises a plurality of first conductive lines, the conductive redistribution layer of the conductive redistribution layer structure comprises a plurality of second conductive lines, at least some of the first conductive lines of the die are, in a top view, parallel to the second conductive lines of the fan-out substrate, and in the top view, an area of a total of regions where the first conductive lines of the interconnect layer of the die are overlapped with the second conductive lines of the conductive redistribution layer of the fan-out substrate is smaller than a preset value determined by an integrated fan-out package performance according to capacitance and inductance information or a coupling effect between the die and the fan-out substrate, wherein the plurality of first conductive bumps and the plurality of second conductive bumps are overlapped with each of the fan-out substrate and the die.

15. The integrated fan-out package of claim 14, further comprising a dielectric layer encapsulating the first conductive bumps, wherein a dielectric constant of the dielectric layer is equal to or less than about 3.

16. The integrated fan-out package of claim 14, wherein an aspect ratio of the second conductive bumps is the same as the aspect ratio of the first conductive bumps.

17. The integrated fan-out package of claim 14, wherein an aspect ratio of the second conductive bumps is different from the aspect ratio of the first conductive bumps.