Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays

• US 10,121,553 B2
• Filed: 08/26/2016
• Issued: 11/06/2018
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Harari, Eli
• Primary Examiner(s): Tran, Uyen B
• Assistant Examiner(s): Leboeuf, Jerome
• Application Number:
  US15/248,420
• Publication Number:
  US 20170092371A1
• Time in Patent Office: 802 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/78633 with a light shield
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/92 Capacitors having potential barriers
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.

Claims

1. A memory structure, comprising:

a semiconductor substrate having a substantially planar surface, wherein the semiconductor substrate has circuitry formed therein;

a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance along a first direction, wherein each stack of active strips comprises two or more active strips provided one on top of another on two or more isolated planes and being substantially aligned lengthwise with each other along a second direction substantially parallel to the planar surface, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between a second semiconductor layer and a third semiconductor layer each of a second conductivity type, the first, second and third semiconductor layers each comprise polysilicon or silicon germanium;

a charge-trapping material; and

a plurality of conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being within a group of the conductors that are provided between the first stack of active strips and the second stack of active strips and separated from each stack of active strips by the charge-trapping material, thereby forming in each active strip at least one NOR string, each NOR string including a plurality of thin film transistors, including two or more thin-film transistors, that are formed out of the first, the second and the third semiconductor layers of the active strip and their adjacent charge-trapping material and the conductors within the group, wherein (a) the first, second and third semiconductor layers in each active strip provide, respectively, channel, source and drain regions of the thin-film transistors, (b) the thin-film transistors of each active strip sharing source and drain regions in common, and (c) one of the shared source and shared drain regions is electrically isolated relative to the circuitry, except when one or more of a selected group of thin-film transistors formed in the active strip are rendered conducting to charge a parasitic or intrinsic capacitor of the electrically isolated shared region by a current through the other shared region to a predetermined voltage.

2. The memory structure of claim 1, wherein the predetermined voltage is a voltage related to one of:

program, program-inhibit, reading and erasing data operations of the thin-film transistors.

3. The memory structure of claim 2, wherein the second semiconductor layer serves as a shared virtual voltage source and the third semiconductor layer serves as a common bit line for the thin-film storage transistors in each NOR string.

4. The memory structure of claim 1, further comprising a second plurality of conductors formed along the first direction, the second plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors that serve as gate electrodes of the thin-film transistors.

5. The memory structure of claim 4, wherein the second plurality of conductors are formed between the planar surface and the active strips, the memory structure further comprising a third plurality of conductors formed above the active strips along the first direction, the third plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors that serve as gate electrodes of the thin-film transistors.

6. The memory structure of claim 5, wherein the selected ones of the first plurality of conductors that are connected to the second plurality of conductors and the selected ones of the first plurality of conductors that are connected to the third plurality of conductors are provided on opposite sides of an active strip.

7. The memory structure of claim 5, wherein each thin-film storage transistor is associated with a numeric address, wherein the thin-film transistors associated with even addresses are connected to the second plurality of conductors and wherein the thin-film transistors associated with odd addresses are connected to the third plurality of conductors.

8. The memory structure of claim 1, wherein each active strip further comprises at least one metallic layer that is in electrical contact with, and in substantial alignment lengthwise with, one or both of the second semiconductor layer and the third semiconductor layer.

9. The memory structure of claim 1 wherein each thin-film storage transistor has a native enhancement mode threshold voltage, for each conductor.

10. The memory structure of claim 9 wherein, during a read or program operation, only the conductor associated with an addressed thin-film storage transistor of a NOR string is raised for a period of time to the predetermined voltage required for the read or program operation, while conductors associated with all other thin-film storage transistors of the NOR string held at a voltage below a threshold voltage of an erased thin-film storage transistor.

11. The memory structure of claim 10, wherein active strips on one or more planes other than on a plane associated with the addressed thin-film storage transistor have their second or third semiconductor layer pre-charged to an inhibit voltage.

12. The memory structure of claim 11, wherein thin-film storage transistors associated with active strips on more than one plane have their respective source regions pre-charged to predetermined voltages and are then programmed in a single concurrent programming operation.

13. The memory structure of claim 12 wherein, during the concurrent programming operation, the second or third semiconductor layer of each active strip in each plane is pre-charged to the predetermined voltage, which is associated with a program or program-inhibit operation, programming voltage pulses are then applied to one or more addressed conductors, and wherein the concurrent programming operation is terminated after all thin-film storage transistors associated with the addressed conductors are read-verified to have reached their respective intended programmed states.

14. The memory structure of claim 12 wherein the second or third semiconductor layer of each active strip in one or more planes is concurrently pre-charged to the predetermined voltage, which is associated with a read operation, prior to carrying out one or more read operations of addressed thin-film storage transistors in one or more of the planes while the second or third semiconductor layer holds substantially the predetermined voltage by virtue of capacitance along its associated active strip.

15. The memory structure of claim 14, wherein the predetermined voltages of active strips on one or more planes serve as virtual ground voltage sources that are electrically isolated from each other, thereby substantially avoiding ground bounce or current spikes when a multiplicity of the addressed thin-film storage transistors are concurrently read.

16. The memory structure of claim 1, wherein data stored in one or more of the thin-film storage transistors have a data retention time shorter than a year and a program/erase cycle endurance greater than 10,000 program/erase cycles.

17. The memory structure of claim 1, wherein data stored in one or more of the thin-film storage transistors represents a continuum of stored states in an analog memory.

18. The memory structure of claim 1, wherein the electric charge in the charge-trapping material in each thin-film storage transistor is provided from one of the first, second and third semiconductor layers through a direct tunneling or a Fowler-Nordheim tunneling mechanism, or through channel hot-electron injection.

19. The memory structure of claim 18, wherein the electric charge in each thin-film storage transistor sets the thin-film storage transistor to a threshold voltage corresponding to one of two or more charge states.

20. The memory structure of claim 1, further comprising a dopant diffusion-blocking layers between the first semiconductor layer and the second semiconductor layer and between the second semiconductor layer and the third semiconductor layer.

21. The memory structure of claim 20, wherein the dopant diffusion-blocking layer comprises a dielectric material that is less than three nanometers thick.

22. The memory structure of claim 1, further comprising buried contact structures to connect one of the second and third semiconductor layers of each active strip to circuitry at the surface of the semiconductor substrate.

23. The memory structure of claim 1, further comprising electrically conductive material providing shielding between thin film transistors on adjacent NOR strings.

24. The memory structure of claim 1, wherein the channel region of each thin-film storage transistor is connected to the semiconductor substrate by a pillar of semiconductor material of the first conductivity type.

25. The memory structure of claim 24, wherein the semiconductor substrate provides the channel region of each thin-film storage transistor through the pillar a predetermined back bias voltage that suppresses sub-threshold leakage during a read operation or an erase voltage during an erase operation.

26. The memory structure of claim 24, wherein the semiconductor substrate applies to the channel region of each thin-film storage transistor one or more erase voltage pulses during block erase operations, while all the first plurality of conductors are held at a ground voltage.

27. The memory structure of claim 1, wherein the source region and the drain regions of each thin-film storage transistor are set to a voltage higher than a threshold voltage for the thin-film storage transistor when in the non-conducting state.

28. The memory structure of claim 1, wherein the second and third semiconductor layers are set to receive one or more erase voltage pulses while the first plurality of conductors are held at ground voltage during a block erase operation.

29. The memory structure of claim 1, wherein the length of the channel region is sufficiently short to effectuate erase through lateral hopping conduction and tunneling out of stored charge under fringing electric fields between the first, second and third semiconductor layers and corresponding ones of the first plurality of conductors.

30. The memory structure of claim 5, wherein each thin-film storage transistor of each NOR string is randomly accessed.

31. The memory structure of claim 30, wherein the thin-film transistors of the semiconductor structure are organized into addressable memory pages each belonging to a corresponding storage plane of adjacent NOR strings, wherein each memory page comprises a thin-film storage transistor from each corresponding storage plane, and wherein thin-film transistors in the storage plane occupy a selected position in each NOR string of the corresponding storage plane.

32. The memory structure of claim 31, wherein the thin-film transistors are organized into addressable memory slices, each memory slice comprising adjacent memory pages each of a different storage plane.

33. The memory structure of claim 32, wherein the thin-film transistors are organized into addressable memory quadrants, each quadrant comprising a plurality of adjacent memory slices.

34. The memory structure of claim 33, wherein the thin-film transistors are organized into memory blocks, each memory block comprising a two-by-two configuration of adjacent memory quadrants.

35. The memory structure of claim 34, wherein thin-film transistors in a first one of the quadrants and a second one of the quadrants share a common set of circuitry at the surface of the semiconductor substrate.

36. The memory structure of claim 32, wherein thin-film transistors on all NOR strings, memory pages or memory slices that are not selected for programming or reading operations are program-inhibited or floated.

37. The memory structure of claim 34 wherein, during an erase operation, selected thin-film transistors of one or more memory blocks are erased together in parallel.

38. The memory structure of claim 34, wherein thin-film transistors in a first group of one or more memory blocks are erased together, while thin-film transistors of a second group of one or more memory blocks are programmed or read together.

39. The memory structure of claim 1, wherein each NOR string is individually addressable, and wherein a thin-film storage transistor in each of a plurality of the NOR strings are programmed, erased, and read simultaneously.

40. The memory structure of claim 3, wherein the shared virtual voltage source of the NOR string allows a thin-film storage transistor to be programmed, program-inhibited, erased or read.

41. The memory structure of claim 32, wherein randomly addressed memory pages or memory slices are programmed in an operation that also includes an erasing step.

42. The memory structure of claim 40, wherein the shared virtual voltage source does not vary in voltage by more than a predetermined amount during programming, program-inhibition, erase and read of the thin-film storage transistor.

43. The memory structure of claim 1, wherein the circuitry at the surface of the semiconductor substrate charges the intrinsic capacitor selectively to one of:

a read voltage, a program voltage, a program-inhibit voltage, an erase voltage, or voltages for setting the programmable thin film transistors of NOR strings designated as reference strings.

44. The memory structure of claim 43 wherein, during a read operation of a selected thin-film storage transistor in each of a selected plurality of NOR strings, (i) the selected group of thin-film transistors in each of the selected NOR strings charge the intrinsic capacitor of the floating one of the second and third semiconductor layers of the NOR string to a predetermined voltage from the circuitry at the surface of the semiconductor substrate;

(ii) thereafter, the other one of the second and third semiconductor layers of each selected NOR string is charged to a read-sense voltage and is connected to a sense amplifier in the circuitry at the surface of the semiconductor substrate; and

(iii) corresponding ones of the first plurality of conductors associated with the selected thin-film transistors are set to a sequence of predetermined read voltages or a voltage ramp while all unselected conductors of the first plurality of conductors are held in their non-conducting state.

45. The memory structure of claim 44, further comprising one or more contacts provided to connect selectively the shared drain region of each NOR string through selection decoders to circuitry at the surface of the substrate.

46. The memory structure of claim 1 wherein, during a programming operation, intrinsic capacitors of the source region, the drain region and the channel region of a selected thin-film storage transistor are each momentarily pre-charged to a virtual ground voltage.

47. The memory structure of claim 46, wherein one or more programming voltage pulses are applied to corresponding one of the first plurality of conductors to initiate efficient Fowler-Nordheim tunneling or direct tunneling of charge from the source, drain and channel regions to the charge-trapping material, while all other ones of the first plurality of conductors are held at a voltage that inhibits initiation of efficient Fowler-Nordheim tunneling or direct tunneling of charge from the corresponding source, drain and channel regions to the charge-trapping material.

48. The memory structure of claim 47, wherein the programming operation is interrupted after a predetermined time and a program-verify read operation is carried out on the selected thin-film transistor.

49. The memory structure of claim 48, wherein upon verification that the selected thin-film storage transistor is correctly programmed, the intrinsic capacitors of the source, drain and channel regions are charged to a program-inhibit voltage to prevent further programming, while continuing to apply the programming voltage pulses to the selected conductor until thin-film transistors on other NOR strings that share the selected conductor are verified to be correctly programmed.

50. The memory structure of claim 34, wherein the channel region of each thin-film storage transistor is connected to the semiconductor substrate by a pillar of semiconductor material of the first conductivity type, and wherein all thin-film transistors of all NOR strings in one or more memory blocks are erased in a single operation by applying one or more erase voltage pulses to the pillars, while holding the conductors in the first plurality of conductors at ground potential.

51. The memory structure of claim 31, wherein one or more spare NOR strings are provided in each storage plane for replacing any one of a plurality of NOR strings in the same storage plane.

52. The memory structure of claim 31, wherein one or more of the storage planes are designated redundant planes, the redundant planes providing spare NOR strings for replacing NOR strings in the other storage planes, or for replacing memory pages on the other storage planes.

53. The memory structure of claim 34, wherein the charged intrinsic capacitors are refreshed in the background in a standby mode or charging is initiated for selected memory blocks in anticipation of impending read operations, so as to allow a fast subsequent concurrent read or a fast subsequent random accessed read of thin-film transistors in one or more memory pages on one or more storage planes.

54. The memory structure of claim 12, wherein, during an erase operation, a voltage on the intrinsic capacitor of each active strip imposed from the circuitry at the surface of the substrate is further boosted to a predetermined erase voltage by raising a voltage on each of a plurality of unselected ones of the first plurality of conductors, while keeping a voltage on corresponding ones of the first plurality of conductors that are selected for erase at another predetermined voltage.

55. The memory structure of claim 12, wherein each active strip comprises a first NOR string formed along one side of the active strip and a second NOR string formed along the other side of the active strip, wherein, one of the first plurality of conductors is located between the first NOR string of a first active strip and the second NOR string of a second active strip, and wherein the intrinsic capacitor of the first NOR string of the first active strip is charged to a programming voltage, while the intrinsic capacitor of the second active strip is charged to a program-inhibit voltage.

56. The memory structure of claim 55, wherein the one of the first plurality of conductors is applied pulses of one or more programming voltages or a ramp of successively higher programming voltages.

57. The memory structure of claim 56, wherein the pulses of programming voltages are made successively higher and, between the pulses of programming voltages, the thin-film storage transistor associated with that one of the conductors is read.

58. The memory structure of claim 57, wherein the pulses of programming voltages are stopped when reading the thin-film storage transistor indicates that it has been programmed to its intended threshold voltage and wherein, thereafter, the intrinsic capacitor of the first NOR string is charged to a predetermined program-inhibit voltage.

59. The memory structure of claim 58, wherein each pulse of the programming voltages corresponds to a threshold voltage in the thin-film storage transistor under a multi-bit storage scheme.

60. The memory structure of claim 55, wherein the intrinsic capacitor of the first NOR string of the first active strip is charged to a program-inhibit voltage upon read-verification that a selected one of the thin-film storage transistors associated with that one of the first plurality of conductors is in their correctly programmed state.

61. The memory structure of claim 12 wherein, during a programming operation of a selected thin-film storage transistor in each of a selected plurality of NOR strings, the selected group of thin-film transistors in each of the selected NOR strings charge the intrinsic capacitor of the floating one of the second and third semiconductor sublayers of the NOR string successively to one of a plurality of predetermined voltages from the circuitry at the surface of the semiconductor substrate, each predetermined voltage being one of a plurality of intended threshold voltage states for the selected thin-film transistors.

62. The memory structure of claim 34, wherein multiple selected active strips on one or more storage planes on one or more memory blocks are charged to provide virtual voltage sources for these multiple selected active strips so as to allow concurrent or sequential programming or program-inhibition or erase operations in parallel.

63. The memory structure of claim 31, wherein selected thin-film transistors in active strips within a memory page are programmed, program-inhibited, or read concurrently.

64. The memory structure of claim 32, wherein selected thin-film transistors that are within a memory slice are programmed, program-inhibited, read or erased concurrently.

65. The memory structure of claim 32, further comprising one or more sense amplifiers for concurrently reading the data stored in selected thin-film transistors from one or more memory pages in a memory slice.

66. The memory structure of claim 34, wherein the intrinsic capacitors of multiple active strips on one or more storage planes in one or more selected memory blocks are charged to predetermined voltage conditions prior to concurrently reading the thin-film transistors associated with the multiple active strips.

67. The memory structure of claim 34, wherein the intrinsic capacitors of multiple active strips on one or more storage planes in one or more selected memory blocks are charged to predetermined voltage conditions prior to sequentially reading the thin-film transistors associated with the multiple active strips.

68. The memory structure of claim 12, wherein the circuitry at the surface of the semiconductor substrate comprises a data integrity circuit which, upon detecting an error, communicates the error to an on-chip error correcting circuitry or to an external system controller, thereby enabling the on-chip circuitry or the external system controller to carry out a data recovery and program-refresh operation.

69. The memory structure of claim 12, wherein the circuitry at the surface of the semiconductor substrate comprises interface circuits that allows direct access to the second set of input/output ports for random access to the thin-film transistors under one or more conventional DRAM, SRAM, NOR flash, NAND flash, Flash solid state drive, word-wide or serial bit steaming protocols.

70. The memory structure of claim 69, wherein the memory circuit performs a read-refresh or program-refresh operation on a portion of the thin-film transistors in a background mode, while carrying out concurrently read, program, or erase operations in a second portion of the thin-film transistors and powering down a third portion of the thin-film transistors.

71. The memory structure of claim 1, wherein the charge-trapping material has a tunneling dielectric layer less than 3 nm thick to initiate tunneling of charge from the first semiconductor layer into the charge-trapping layer through a direct tunneling or through a Fowler-Nordheim tunneling mechanism.

72. The memory structure of claim 32, wherein each active strip comprises a first NOR string formed along one side of the active strip and a second NOR string formed along the other side of the active strip, wherein the conductors between the first NOR string of a first active strip and the second NOR string of an adjacent active strip serve as shared gate electrodes between corresponding thin-film transistors of the first NOR string and the second NOR string, thereby forming related transistor pairs, wherein the thin-film transistors of the first NOR string serve as reference transistors for corresponding thin-film transistors in the second NOR string, wherein each reference transistor holds a programmed state when the other of the related transistor pair holds an erased state, and vice versa, and wherein output signals from the thin-film transistors of a related transistor pair are fed simultaneously into a differential sense amplifier to determine the data represented by the output signals.

73. The memory structure of claim 72, wherein the thin-film transistors in each related transistor pair reverses roles in successive programming operations to substantially equalize cumulative degradations.

74. The memory structure of claim 73, wherein thin-film storage transistors in one or more memory pages or memory slices within a predetermined distance from the circuitry at the surface of the semiconductor substrate are configured to operate as related transistor pairs (“

high speed configuration”

).

75. The memory structure of claim 74, wherein the remainder of the pages or slices are configured to operate with one reference transistor for two or more thin-film transistors (“

low cost configuration”

) within the memory pages or slices.

76. The memory structure of claim 75 wherein, under the low cost configuration, more than one binary bit of information is stored in each thin-film storage transistor and wherein more than one reference NOR string is provided to read the stored multibit information.

77. The memory structure of claim 74, wherein the thin-film transistors operating under the high-speed configuration store on-chip resource management data for use by an external controller.

78. The memory structure of claim 77, wherein the on-chip resource management data includes one or more of:

an updatable file allocation table for files stored in the memory circuit, a unique identifier index number, a program/erase cycle count, chip temperature, and a time-stamp that is appended to each stored data file when it is updated.

79. The memory structure of claim 74, wherein the circuitry at the surface of the substrate further comprises a pipeline streaming circuitry that overlaps sensing a memory page of stored data in sense amplifiers and transferring the sensed data to a data buffer for serial bit stream, or parallel word-wide output from the memory circuit, with concurrently reading a next memory page of the stored data from the memory structure for sensing in the sense amplifies.

80. The memory structure of claim 79, wherein the data buffer is provided within a portion of the memory structure operating under the high speed configuration, while the next page of the file is being read from a portion of the memory circuit operating under low cost configuration.

81. The memory structure of claim 32, wherein thin-film transistors in one or more memory pages or memory slices within a predetermined distance from the circuitry at the surface of the semiconductor substrate are designated to operate as cache storage.

82. The memory structure of claim 1, wherein the first semiconductor layer is provided in cavities or recesses that result from removal of all or part of a sacrificial layer.

83. The memory structure of claim 82, wherein the first semiconductor layer has a width that is independent of the widths of the second and third semiconductor sublayers.

84. The memory structure of claim 82, wherein the first semiconductor layer of each active strip is substantially the same for all active strips aligned along the second direction.

85. The memory structure of claim 82, wherein the first semiconductor sublayer has a thickness that is sufficiently thin to be readily depleted when a voltage is applied between the conductors and the second and third semiconductor sublayers.

86. The memory structure of claim 82, wherein the channel region of each thin-film storage transistor has a length substantially determined by a thickness of the sacrificial layer removed.

87. The memory structure of claim 82, wherein the channel region of each thin-film storage transistor has a length that is sufficiently short to accelerate the erase operation by removal of charge trapped in the charge-trapping material adjacent the channel region, assisted by fringing-field-aided lateral hopping conduction of charge within the charge-trapping layer, when a predetermined voltage is applied between the gate terminal and the source and drain regions during the erase operation.

88. The memory structure of claim 3, further comprising one or more reference strings set to one or more reference threshold levels to facilitate correctly program, erase and read the NOR strings.

89. The memory structure of claim 88, wherein the circuitry in the semiconductor substrate comprises differential sense amplifiers each comparing a signal received from a selected thin-film storage transistor of a selected NOR string and a signal from one of the reference NOR strings.

90. The memory structure of claim 88, wherein each of the NOR strings and each of the reference strings have approximately the same background leakage current between their respective shared source and drain regions, and wherein when a thin-film storage transistor of one of the NOR strings is selected for a read operation, one of reference strings is also selected, such that the background leakage current of selected reference string substantially neutralizes the background leakage current of one of the selected NOR strings.

91. The memory structure of claim 3, wherein each NOR string is configured to serve as its own reference string for correcting background leakage current, according to:

(i) in a first step, sensing both a background leakage current of the NOR string and a read current of an addressed thin-film storage transistor of the NOR string, and (ii) sensing the background leakage current of the NOR string.

92. The memory structure of claim 88, wherein one or more of the thin-film transistors of the reference string are programmed to have set reference threshold voltages that are used to correctly program and correctly read the threshold voltages of the selected NOR string.

93. The memory structure of claim 88, wherein selected ones of the thin-film transistors in the reference NOR string are programmed to have set reference threshold voltages that are used to correctly program and correctly read the threshold voltages of corresponding thin-film transistors of a NOR string selected for a programming or read operation.

94. The memory structure of claim 88, wherein the memory structure is organized into a plurality of storage planes, and wherein the reference strings are designated to operate with a selected plurality of NOR strings, the reference strings and the reference strings being provided on the same storage plane or wherein the reference strings are provided on a designated storage plane (“

reference plane”

).

95. The memory structure of claim 94, wherein each storage plane comprises won or more memory pages, and wherein signals from thin-film transistors in a selected memory page in the reference plane and signals from corresponding thin-film transistors in a memory page of a selected NOR string are sensed in corresponding sense amplifiers in the circuitry at the surface of the semiconductor substrate.

96. The memory structure of claim 94, wherein one or more NOR strings in the reference plane are designated spare NOR strings, each spare NOR string being configurable to replace a NOR string outside of the reference plane.

97. The memory structure of claim 88, wherein the memory structure is organized into a plurality of memory slices, wherein one or more memory slices are designated reference slices for the other memory slices in the memory structure and wherein one or more of the thin-film transistors of each reference slice are programmed to have set reference threshold voltages that are used to correctly program and correctly read the threshold voltages of corresponding thin-film transistors in the other slices.

98. The memory structure of claim 88, wherein one or more of the reference NOR strings provide a set of reference voltages suitable for programming and reading operations under a multi-bit scheme.

99. The memory structure of the claim 88, wherein the circuitry at the surface of the semiconductor substrate provides the source and drain regions of thin-film transistors of the reference NOR string successively a range of voltages to be used for detecting the programmed voltage stored on the corresponding thin-film transistors in the selected NOR string.

100. The memory structure of claim 34, wherein each thin-film storage transistor in a reference string is programmed to provide a first reference voltage, and wherein, during a programming or reading operation, the circuitry at the surface of the semiconductor substrate adjusts the voltages at the shared source and drain regions of that thin-film storage transistor in the reference string according to a set or a continuum of additional reference voltages, so as to provide correct programming and reading voltages to corresponding thin-film transistors in the selected NOR string under a multi-bit or analog data scheme.

101. The memory structure of claim 100, wherein the leakage current in reference NOR strings or selected NOR strings is minimized by modulating the voltages on the common source region and the common drain region of thin-film transistors in the reference strings and the selected NOR strings.