Multi-gate nor flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates

• US 10,121,554 B2
• Filed: 12/19/2017
• Issued: 11/06/2018
• Est. Priority Date: 09/30/2015
• Status: Active Grant

• Current Assignee: Sunrise Memory Corporation
• Original Assignee: Sunrise Memory Corporation
• Inventors: Harari, Eli
• Primary Examiner(s): Dinh, Son
• Assistant Examiner(s): Leboeuf, Jerome
• Application Number:
  US15/846,766
• Publication Number:
  US 20180108423A1
• Time in Patent Office: 322 Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.

Claims

1. A NOR string array formed over a planar surface of a semiconductor substrate, comprising a first NOR string and a second NOR string, each NOR string comprising thin-film storage transistors formed along an active strip extending lengthwise along a first direction parallel to the planar surface, wherein the thin film storage transistors in each NOR string share a pre-charge device, a common drain terminal and a common source terminal, wherein a gate terminal of each storage transistor in the first NOR string is electrically connected to a gate terminal of a corresponding storage transistor in the second NOR string by a conductor that extends lengthwise along a second direction which is substantially perpendicular to the planar surface, and wherein the pre-charge device pre-charges the common source terminal to a voltage that is substantially held by virtue of a parasitic capacitance in the source terminal during a program, program-inhibit, reading or erasing operation on the NOR string, further comprising a third NOR string, wherein the first NOR string and the third NOR string are formed on a plane parallel the planar surface, wherein one or more storage transistors on the third NOR string are programmed to have reference threshold voltages, which are compared to threshold voltages of storage transistors in the first NOR string during programming or read operations.

2. The NOR string array of claim 1, wherein the active strip of the first NOR string and the active strip of the second NOR string are both formed on a plane parallel to the planar surface.

3. The NOR string array of claim 1, wherein the third NOR string provides a reference string leakage current source by setting all the storage transistors of the third NOR string are in an off state.

4. The NOR string array of claim 1, further comprising a plurality of reference NOR strings, wherein when the storage transistors of the first NOR string are programmed according to a multibit scheme, the reference NOR strings each provide a reference for a different state of the multibit scheme.

5. The NOR string array of claim 1, wherein the conductor comprises one of N⁺ doped polysilicon, P⁺ doped polysilicon, and a refractory metal of a high work function with respect to silicon dioxide.

6. The NOR string array of claim 1, wherein the common drain terminal comprises a semiconductor layer and a metallic layer that is in electrical contact with, and in substantial alignment lengthwise with, the semiconductor layer.

7. The NOR string array of claim 1, wherein each active strip has a first side-edge and a second side-edge on opposite sides of the active strip, wherein an independently controlled NOR string is formed along each side-edge.

8. The NOR string array of claim 1, further comprising a first global wiring which is in electrical contact with the conductor and which extends lengthwise along a third direction that is substantially orthogonal to both the first and second direction.

9. The NOR string array of claim 8, wherein support circuitry for memory operations is formed on or in the semiconductor substrate and wherein the first global wiring conducts electrical signals from the support circuitry to the conductor.

10. The NOR string array of claim 9, wherein the support circuitry comprises voltage sources for providing the configurations of voltages to be imposed on the terminals of each storage transistors, so as to effectuate program charging, program-inhibit charging, reading or erasing data stored in the storage transistor.

11. The NOR string array of claim 8, wherein the first global wiring is formed between the semiconductor substrate and the active strip of the first NOR string.

12. The NOR string array of claim 8, wherein the NOR string array further comprises a second global wiring formed above the active strip of the first NOR string, the first and second global wirings are in electrical contact with gate terminals of different storage transistors of the first NOR string.

13. The NOR string array of claim 1, wherein the pre-charge device equalizes the voltages of the common source terminal and the common drain terminal.

14. The NOR string array of claim 12, wherein the common drain terminal is charged to one of several predetermined voltages prior to turning on the pre-charge device, the predetermined voltage being selected from one of:

program, program-inhibit, reading and erasing data of the storage transistors.

15. The NOR string array of claim 1, wherein the common source terminal serves as a shared virtual ground reference and the common drain terminal serves as a common bit line for the storage transistors in each NOR string.

16. A NOR string array formed over a planar surface of a semiconductor substrate, comprising a first NOR string and a second NOR string, each NOR string comprising thin-film storage transistors formed along an active strip extending lengthwise along a first direction parallel to the planar surface, wherein the thin film storage transistors in each NOR string share a pre-charge device, a common drain terminal and a common source terminal, wherein a gate terminal of each storage transistor in the first NOR string is electrically connected to a gate terminal of a corresponding storage transistor in the second NOR string by a conductor that extends lengthwise along a second direction which is substantially perpendicular to the planar surface, and wherein the pre-charge device pre-charges the common source terminal to a voltage that is substantially held by virtue of a parasitic capacitance in the source terminal during a program, program-inhibit, reading or erasing operation on the NOR string, wherein the first NOR string and the second NOR string are formed on first and second planes parallel to the planar surface, respectively, the NOR string array further comprising one or more reference NOR strings on each of the first and second planes, and wherein for each of the reference NOR strings, one or more storage transistors on the reference NOR string are programmed to have reference threshold voltages, which are compared during programming and read operations to threshold voltages of storage transistors in the corresponding NOR string on the same plane as the reference NOR string.