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Multi-gate nor flash thin-film transistor strings arranged in stacked horizontal active strips with vertical control gates

  • US 10,121,554 B2
  • Filed: 12/19/2017
  • Issued: 11/06/2018
  • Est. Priority Date: 09/30/2015
  • Status: Active Grant
First Claim
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1. A NOR string array formed over a planar surface of a semiconductor substrate, comprising a first NOR string and a second NOR string, each NOR string comprising thin-film storage transistors formed along an active strip extending lengthwise along a first direction parallel to the planar surface, wherein the thin film storage transistors in each NOR string share a pre-charge device, a common drain terminal and a common source terminal, wherein a gate terminal of each storage transistor in the first NOR string is electrically connected to a gate terminal of a corresponding storage transistor in the second NOR string by a conductor that extends lengthwise along a second direction which is substantially perpendicular to the planar surface, and wherein the pre-charge device pre-charges the common source terminal to a voltage that is substantially held by virtue of a parasitic capacitance in the source terminal during a program, program-inhibit, reading or erasing operation on the NOR string, further comprising a third NOR string, wherein the first NOR string and the third NOR string are formed on a plane parallel the planar surface, wherein one or more storage transistors on the third NOR string are programmed to have reference threshold voltages, which are compared to threshold voltages of storage transistors in the first NOR string during programming or read operations.

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