Interconnects fabricated by hydrofluorocarbon gas-assisted plasma etch
First Claim
Patent Images
1. An integrated circuit, comprising:
- a plurality of semiconductor devices; and
a plurality of conductive lines connecting the plurality of semiconductor devices, wherein a pitch of the plurality of conductive lines is approximately twenty-eight nanometers, wherein each of the plurality of conductive lines comprises;
a line of a conductive metal; and
a carbon-containing layer positioned directly between the conductive metal and a dielectric material.
2 Assignments
0 Petitions
Accused Products
Abstract
In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.
29 Citations
19 Claims
-
1. An integrated circuit, comprising:
-
a plurality of semiconductor devices; and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein a pitch of the plurality of conductive lines is approximately twenty-eight nanometers, wherein each of the plurality of conductive lines comprises; a line of a conductive metal; and a carbon-containing layer positioned directly between the conductive metal and a dielectric material. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. An integrated circuit, comprising:
-
a front end, comprising; a semiconductor wafer; and a plurality of semiconductor devices formed on the semiconductor wafer; and a back end, comprising; a dielectric layer; a plurality of conductive lines formed in the dielectric layer, wherein a pattern density of the plurality of conductive lines has a pitch of approximately twenty-eight nanometers; and a carbon-containing layer positioned directly between the dielectric layer and each conductive line of the plurality of conductive lines. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
-
-
18. An integrated circuit, comprising:
-
a front end, comprising; a semiconductor wafer; and a plurality of semiconductor devices formed on the semiconductor wafer; and a back end, comprising; a dielectric layer; a plurality of conductive lines formed in the dielectric layer, wherein the plurality of conductive lines has a uniform profile and a pattern density of the plurality of conductive lines has a pitch of approximately twenty-eight nanometers; a carbon-containing layer positioned directly between the dielectric layer and each conductive line of the plurality of conductive lines; and a capping layer positioned directly between the dielectric layer and the front end. - View Dependent Claims (19)
-
Specification