Method of fabricating a post-passivation interconnect structure

• US 10,121,749 B2
• Filed: 04/03/2017
• Issued: 11/06/2018
• Est. Priority Date: 12/07/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsien-Wei, Tsai, Hao-Yi, Lii, Mirng-Ji, Yu, Chen-Hua
• Primary Examiner(s): Malsawma, Lex
• Assistant Examiner(s): Ida, Geoffrey
• Application Number:
  US15/477,717
• Publication Number:
  US 20170338188A1
• Time in Patent Office: 582 Days
• CPC Class Codes: H01L 2224/02235 Reinforcing structures
• CPC Class Codes: H01L 2224/02255 Shape of the auxiliary member
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05181 Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/05186 with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12042 : LASER

Abstract

A method of fabricating a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

Claims

1. A method of fabricating a semiconductor device, comprising:

providing a semiconductor substrate comprising circuitry and a plurality of metal layers formed between dielectric layers operable to route electrical signals formed therein;

forming a passivation layer overlying the semiconductor substrate;

patterning the passivation layer to form a first opening, wherein a conductive pad is disposed under the first opening;

depositing a polymer layer over the passivation layer and a portion of the conductive pad;

forming a conductive layer on the polymer layer;

patterning the conductive layer to form a landing pad region electrically connected to the conductive pad and a plurality of dummy regions electrically separated from the landing pad region, wherein the plurality of dummy regions surround the landing pad region in a plan view;

depositing a metal layer on the substrate over the conductive layer;

patterning the metal layer to form an under-bump-metallization (UBM) electrically connected to the landing pad region and to form a plurality of pillars having each pillar of the plurality of pillars overlying a respective one of the plurality of dummy regions; and

forming a bump over the UBM, wherein the bump is the only bump surrounded by the plurality of pillars is the single bump.

2. The method of claim 1, wherein the forming the conductive layer includes depositing copper.

3. The method of claim 1, wherein depositing the polymer layer over the portion of the conductive pad includes forming an interface between the polymer layer and the conductive pad.

4. The method of claim 1, wherein the patterning the passivation layer to form the first opening includes providing the patterned passivation layer covering a peripheral portion of the conductive pad and exposing a central portion of conductive pad.

5. The method of claim 1, wherein the depositing the polymer layer includes depositing at least one of epoxy, polyimide, benzocyclobutene (BCB), or polybenzoxazole (PBO).

6. The method of claim 1, wherein the depositing the polymer is performed by spin coating.

7. The method of claim 1, wherein the patterning the conductive layer to form the landing pad region and the plurality of dummy regions forms the landing pad region and the plurality of dummy regions simultaneously.

8. The method of claim 1, wherein the patterning the conductive layer to form the landing pad region and the plurality of dummy regions forms the landing pad region and the plurality of dummy regions of a same conductive material.

9. A method of fabricating a semiconductor device, comprising:

forming a passivation layer overlying a semiconductor substrate;

forming a conductive layer over the semiconductor substrate and the passivation layer;

patterning the conductive layer to form a landing pad region and a plurality of dummy regions electrically separated from the landing pad region, wherein the plurality of dummy regions surround the landing pad region in a plan view;

depositing a conductive pillar over each of the plurality of dummy regions of the conductive layer; and

forming a bump over the substrate and connected to the landing pad region, wherein each of the conductive pillars is spaced a same distance from the bump.

10. The method of claim 9, further comprising:

forming an under bump metallization (UBM) over the substrate and the patterned conductive layer, wherein the UBM is electrically connected to the landing pad region.

11. The method of claim 10, wherein the bump is formed on the UBM.

12. The method of claim 9, wherein the patterning the conductive layer to form the plurality of dummy regions includes forming a plurality of at least one of square-shape regions, circle-shape regions, rectangular-shape regions, or slots.

13. The method of claim 9, wherein after patterning the conductive layer and prior to depositing the conductive pillars, forming a protective layer over at least a portion of the patterned conductive layer.

14. The method of claim 13, wherein the protective layer interfaces with a top surface of each of the plurality of dummy regions of the patterned conductive layer.

15. The method of claim 9, wherein the depositing the conductive pillar over each of the plurality of dummy regions includes:

depositing a metal layer;

patterning the metal layer to form the conductive pillar over each of the plurality of dummy regions and form an under-bump-metallization (UBM) layer.

16. A method of fabricating a semiconductor device, comprising:

forming a passivation layer overlying a semiconductor substrate;

forming a first conductive layer over the passivation layer;

patterning the first conductive layer to form;

a first landing pad region and a first plurality of dummy regions electrically separated from the first landing pad region, wherein the first plurality of dummy regions surround the first landing pad region in a plan view;

a second landing pad region and a second plurality of dummy regions electrically separated from the second landing pad region, wherein the second plurality of dummy regions surround the second landing pad region in a plan view, the second plurality of dummy regions are different than the first plurality of dummy regions;

depositing a second conductive layer on the substrate over the first conductive layer;

patterning the second conductive layer to form;

a first under-bump-metallization (UBM) electrically connected to the first landing pad region, a second UBM electrically connected to the second landing pad region, a first plurality of pillars having each pillar of the first plurality of pillars overlying a respective one of the first plurality of dummy regions, and a second plurality of pillars having each pillar of the second plurality of pillars overlying a respective one of the second plurality of dummy regions; and

forming a first bump over the first UBM and a second bump over the second UBM, wherein the first plurality of pillars surrounds the first bump in the plan view and the second plurality of pillars surrounds the second bump in the plan view.

17. The method of claim 16, wherein the first bump is a next adjacent bump to the second bump in the plan view.

18. The method of claim 16, wherein each of the first plurality of pillars that surrounds the first bump is spaced a first distance from the first bump.

19. The method of claim 16, wherein the depositing the second conductive layer includes one of titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN).

20. The method of claim 19, wherein the depositing the second conductive layer includes depositing a seed layer.